Wafer scale package and method of assembly

• US 6,939,784 B2
• Filed: 04/09/2004
• Issued: 09/06/2005
• Est. Priority Date: 03/26/2003
• Status: Expired due to Term

• Current Assignee: Northrop Grumman Systems Corporation (Northrop Grumman Corporation)
• Original Assignee: Northrop Grumman Corporation
• Inventors: Fudem, Howard, Chen, Li-Shu, Smith, Philip C., Moloney, Thomas J.
• Primary Examiner(s): Nguyen, Ha Tran
• Assistant Examiner(s): Geyer, Scott B.
• Application Number:
  US10/820,761
• Publication Number:
  US 20040191957A1
• Time in Patent Office: 515 Days
• Field of Search: 438/106, 438/110, 438/113, 438/125, 438/455, 438/456, 438/458, 438/114, 438/51, 438/55, 438 64- 68
• US Class Current: 438/456
• CPC Class Codes: B81B 2201/018 Switches not provided for in B81B2201/014 - B81B2201/016
• CPC Class Codes: B81B 2207/097 Interconnects arranged on the substrate or the lid, and covered by the package seal
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A plurality of electronic circuits and associated signal lines are positioned at respective locations on a base wafer. A cover wafer, which fits over the base wafer, includes a corresponding like number of locations each including one or more cavities to accommodate the electronic circuit and associated signal lines. The cover wafer includes a plurality of vias for making electrical connection to the signal lines. A multi layer metallic arrangement hermetically seals the periphery of each location as well as sealing the bottom of each via. The joined base and cover wafers may then be diced to form individual die packages.

Claims

1. A method of making a wafer scale package for electronic circuits, comprising the steps of:

placing electronic circuits each having at least one electronic device and associated plurality of signal lines comprised of at least one metal layer at respective circuit locations on a base wafer;

forming cavities on an undersurface of a cover wafer at respective circuit locations to accommodate said respective circuit electronic devices, when said wafers are joined;

forming and metalizing vias in said cover wafer;

applying at least one initial layer of metal in and on an undersurface of said vias and thereby forming via pads;

applying at least one initial layer of metal on a top surface of said base wafer around the periphery of each said location; and

applying at least one initial layer of metal on an undersurface of said cover wafer around the periphery of each said location;

metalizing a periphery of each said circuit location on said base and cover wafers with at least one intermediate layer of metal;

metalizing an electric contact between said via pads and said signal lines with at least one intermediate layer of metal;

wherein the number and thickness of metal layers at the periphery of each said location is substantially equal to the number and thickness of metal layers at said vias and signal lines for ensuring planar alignment of the base and cover wafers when joined together;

joining said base and cover wafers at predetermined pressure, temperature and time conditions to form a peripheral hermetic seal around each said circuit location and a via hermetic seal around each said bottom of said vias; and

dicing said joined and sealed wafers along said locations to provide individual die packages.

2. A method of making a wafer scale package according to claim 1 which includes the step of:

providing a base wafer of quartz.

3. A method of making a wafer scale package according to claim 1 which includes the step of:

providing a cover wafer of quartz.

4. A method of making a wafer scale package according to claim 1 which includes the step of:

joining said base and cover wafers at a pressure of around 30 to 80 psi.

5. A method of making a wafer scale package according to claim 1 which includes the step of:

joining said base and cover wafers at a temperature of around 120°

C. to 200°

C.

6. A method of making a wafer scale package according to claim 1 which includes the step of:

joining said base and cover wafers at said predetermined pressure and temperature for around 1 to 3 hours.

7. A method of making a wafer package according to claim 1 wherein said base wafer and said cover wafer are comprised of quartz.

8. A method of making a wafer scale package according to claim 7 wherein said at least one initial layer of metal on the surface of said vias, the top surface of said base wafer and the undersurface of said cover wafer comprises a layer of titanium for enhancing adhesion to said quartz wafers and said vias.

9. A method of making a wafer scale package according to claim 1 wherein said at least one intermediate layer of metal at each said periphery and each of said via pads comprise a plurality of intermediate metal layers including adjacent layers of indium and nickel which fuse so as to become a strength enhancing indium-nickel alloy upon joining said base and cover wafers.

10. A method of making a wafer scale package according to claim 9 and additionally including at least one outer layer of metal adjacent the indium layer and the nickel layer of said intermediate layers.

11. A method of making a wafer scale package according to claim 9 and additionally including an outer layer of metal respectively adjacent the indium layer and the nickel layer of said intermediate layers.

12. A method of making a wafer scale package according to claim 9 wherein the base wafer and cover wafer include at least one additional layer of metal between the respective layers of titanium and said intermediate layers.

14. A method according to claim 11 and additionally including the step of:

dicing said joined and sealed wafers along said locations to provide individual die packages.

13. A method of making a wafer scale package for electronic circuits, comprising the steps of:

placing electronic circuits each having at least one electronic device and associated signal lines at respective circuit locations on a base wafer comprised of quartz;

forming cavities on an undersurface of a cover wafer comprised of quartz at respective circuit locations to accommodate said respective circuit electronic devices, when said wafers are joined;

forming vias in said quartz cover wafer;

applying an initial metal layer of titanium on an inner surface and an undersurface of said vias;

applying an initial metal layer of titanium on the top surface of the quartz base wafer around the periphery of each said location; and

applying an initial metal layer of titanium on the undersurface of the quartz cover wafer around the periphery of each said location;

metallizing a periphery of each said location on said base and cover wafers with a plurality of intermediate metal layers including adjacent layers of indium and nickel;

metallizing an electric contact between a bottom of a said metallized via and said signal lines with a like number of intermediate metal layers also including adjacent layers of indium and nickel;

wherein the number and thickness of metal layers at the periphery of each said location is substantially equal to the number and thickness of metal layers at said vias and signal lines for ensuring planar alignment of the base and cover wafers when joined together;

joining said base and cover wafers at a pressure of about 30 to 80 psi, at a temperature of about 120°

C. to 200°

C. and for about 1 to 3 hours to form a peripheral hermetic seal around each said circuit location and a via hermetic seal around each said bottom of said via.