Semiconductor device with inductive component and method of making

• US 6,939,788 B2
• Filed: 10/24/2002
• Issued: 09/06/2005
• Est. Priority Date: 08/01/2001
• Status: Expired due to Fees

• Current Assignee: David Richard Stanowski
• Original Assignee: Robert B Davies
• Inventors: Davies, Robert B.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Lee, Calvin
• Application Number:
  US10/279,700
• Publication Number:
  US 20030089963A1
• Time in Patent Office: 1,048 Days
• Field of Search: 257528-532, 257/752, 257/758, 257/277, 438597-599, 438674-678
• US Class Current: 438/599
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

An integrated circuit (10) includes a semiconductor substrate (11) that has a top surface (32) for forming a dielectric region (14) with a trench (40) and one or more adjacent cavities (16). A conductive material such as copper is disposed within the trench to produce an inductor (50). A top surface (49) of the inductor is substantially coplanar with an interconnect surface (31) of the semiconductor substrate, which facilitates connecting to the inductor with standard integrated circuit metallization (57).

Claims

1. A method of making an integrated circuit, comprising the steps of:

forming a dielectric region in a top surface of a semiconductor substrate, where the dielectric region has a cavity;

etching a second surface of the semiconductor substrate to form a recessed region under the dielectric region;

etching the dielectric region to form a trench adjacent to the cavity;

depositing a barrier material to form an etch stop on a bottom surface of the trench; and

disposing a conductive material in the trench to form an inductor.

2. The method of claim 1, wherein the step of etching includes the step of removing dielectric material to a depth of at least five micrometers from the dielectric region.

3. The method of claim 1, wherein the step of disposing includes the step of plating the conductive material within the trench.

4. The method of claim 3, wherein the step of plating includes the step of electroplating copper from a bottom surface of the trench to a top surface of the semiconductor substrate.

5. The method of claim 1, wherein the step of etching the second surface includes the step of removing material from the second surface extending to the etch stop to form the recessed region.

6. The method of claim 5, further comprising the step of mounting the semiconductor substrate to a die attach pad.

7. The method of claim 6, wherein the step of mounting includes the step of mounting the recessed region over a pedestal of the die attach pad.