Memory structures

• US 6,940,085 B2
• Filed: 04/02/2002
• Issued: 09/06/2005
• Est. Priority Date: 04/02/2002
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Van Brocklin, Andrew L., Fricke, Peter, Koll, Andrew, Lazaroff, Dennis M.
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Landau, Matthew C
• Application Number:
  US10/115,744
• Publication Number:
  US 20030183867A1
• Time in Patent Office: 1,253 Days
• Field of Search: 257 2- 4, 257/50, 257/529, 257/530, 257/278, 257/75, 257/315, 257/316, 257/296, 257/314, 257/326, 257/105, 257/301, 257/478, 365/163, 365/174, 365/145, 365/158, 365/170, 365/175, 365/94, 365/96, 365/103, 365/104, 365/105, 365/177
• US Class Current: 257/4
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H10B 61/10 comprising components having two electrodes, e.g. diodes or MIM elements
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices

Abstract

A memory structure that includes a first electrode, a second electrode, a third electrode, a control element disposed between the first electrode and the second electrode, and a memory storage element disposed between the second electrode and the third electrode. At least one of the control element and memory storage element is protected from contamination by at least one of the first electrode, second electrode and third electrode.

Claims

1. A memory comprising:

a first memory structure comprising;

a first conductive region;

a first conductive tub;

a second conductive tub;

a first memory storage element disposed between the first conductive region and the first conductive tub;

a first control element disposed between the first conductive tub and the second conductive tub; and

a first conductive via disposed in the second conductive tub; and

a second memory structure comprising;

a second conductive region;

a third conductive tub;

a fourth conductive tub;

a second memory storage element disposed between the second conductive region and the third conductive tub;

a second control element disposed between the third conductive tub and the fourth conductive tub; and

a second conductive via disposed in the fourth conductive tub and in contact with the first conductive region,

wherein the first memory structure is vertically adjacent the second memory structure.

2. The memory of claim 1, wherein the first memory structure is offset from the second memory structure.

3. The memory structure of claim 1, wherein the first memory storage element is protected from contamination during processing by one of the first conductive region, the first conductive tub, and the second conductive tub, and wherein the second memory storage element is protected from contamination during processing by one of the second conductive region, the third conductive tub, and the fourth conductive tub.

4. The memory structure of claim 1, wherein the first control element is protected from contamination during processing by one of the first conductive region, the first conductive tub, and the second conductive tub, and wherein the second control element is protected from contamination during processing by one of the second conductive region, the third conductive tub, and the fourth conductive tub.

5. The memory structure of claim 1, wherein the first memory storage element comprises an antifuse device.

6. The memory structure of claim 1, wherein the first memory storage element comprises a tunnel junction device.

7. The memory structure of claim 1, wherein the first memory storage element comprises one of an antifuse, a fuse, a charge storage device, a resistive material, a trap-induced hysteresis material, a ferroelectric capacitor material, a Hall effect material, and a tunneling magneto-resistive material.

8. The memory structure of claim 1, wherein the first memory storage element comprises an antifuse including material from the group consisting of an oxidized metal tunnel junction, a silicon dioxide tunnel junction, a dielectric-rupture, a polysilicon semiconductor, a polycrystalline semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, a metal filament electro-migration semiconductor, and a polysilicon resistor semiconductor.

9. The memory structure of claim 1, wherein the first memory storage element comprises a re-writable phase change material.

10. The memory structure of claim 1, wherein the first control element comprises a tunnel junction device.

11. The memory structure of claim 1, wherein the first control element comprises a diode.

12. The memory structure of claim 1, wherein the first control element comprises one of a recrystallized semiconductor, junction field effect transistor, a junction field effect transistor with its gate connected to its source or drain, a four-layer diode, an NPN transistor, and a PNP transistor.

13. The memory structure of claim 1, wherein the first memory storage element is protected from contamination during processing by one of the first conductive region, the second conductive region, the first conductive tub, and the second conductive tub.

14. The memory structure of claim 1, wherein the first control element is protected from contamination during processing by one of the first conductive region, the second conductive region, the first conductive tub, and the second conductive tub.

15. The memory structure of claim 1, wherein the first memory storage element comprises an oxide of a metal of the first conductive region.