Termination structure for a semiconductor device

• US 6,940,145 B2
• Filed: 10/15/2002
• Issued: 09/06/2005
• Est. Priority Date: 10/16/2001
• Status: Active Grant

• Current Assignee: Zetex Plc (Diodes Incorporated)
• Original Assignee: Zetex Plc (Diodes Incorporated)
• Inventors: Blair, Peter, Wood, Andrew, Finney, Adrian, Gerrard, Paul, Mottram, David
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): Erdem, Fazli
• Application Number:
  US10/272,524
• Publication Number:
  US 20030127702A1
• Time in Patent Office: 1,057 Days
• Field of Search: 257/501, 257/510, 257/513, 257/519, 257/520, 257/446, 257/499, 257/395, 257/396, 257/397, 257/398, 257/399, 257/400, 257/487, 257/488, 438/206, 438/208
• US Class Current: 257/510
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device (e.g. MOSFET or IGBT) comprises active and termination regions (1,2) formed in a semiconductor substrate (4). The substrate (4) has an upper surface and a termination including a trench (12) extending into the substrate (4) from the upper surface within the termination region (1). Termination trench (12) is at least partly filled with an insulating material (13) which extends from the termination trench (12) to overlie adjacent regions of the device above the surface. A channel stop region (11) extends laterally from a side wall of the termination trench (12) into the substrate (4).

Claims

1. A semiconductor device comprising active and termination regions formed in a semiconductor substrate having an upper surface, a termination including a trench extending into the substrate from said upper surface within said termination region, wherein said termination trench is at least partly filled with an insulating material which extends from the termination trench to overlie adjacent regions of the device above said surface, and wherein a channel stop region extends laterally from a side wall of the termination trench into the substrate,

wherein said active region comprises at least one trench extending from said upper surface immediately adjacent a body region of a second conductivity type formed below said surface, and a region of substantially the same composition as the channel stop region extending laterally from the active trench into the body region.

2. A semiconductor device according to claim 1, wherein the channel stop region is immediately adjacent said upper surface.

3. A semiconductor device according to claim 1 or claim 2, wherein the channel stop region is of the same conductivity type as the substrate but has a higher dopant concentration than said substrate.

4. A device according to claim 1, wherein said active trench is a gate trench substantially filled with a gate material isolated from the substrate and body regions by a thin layer of gate insulator.

5. A semiconductor device according to claim 4, wherein said termination trench is at least partially lined with a layer of said gate insulator material.

6. A semiconductor device according to claim 5, wherein a lower portion of said termination trench is filled with gate material, said isolation material overlying said gate material within said termination trench.

7. A semiconductor device according to claim 6, wherein the termination trench is of similar width or narrower than the gate trench.

8. A semiconductor device according to claim 5, wherein at most only a small amount of said gate material is present in the termination trench underlying said isolation material.

9. A semiconductor device according to claim 8, wherein there is no gate material present within the termination trench.

10. A semiconductor device according to claim 8 or claim 9, wherein the termination trench is wider than said gate trench.

11. A semiconductor device according to claim 1, wherein the active and termination regions are at least in part separated by a field oxide layer formed on said upper surface of the substrate.

12. A semiconductor device according to claim 1, wherein an oxide layer is supported on the upper surface of said substrate adjacent opposing sides of said termination trench, and said insulating material extends from said termination trench to overlie said oxide layer.

13. A semiconductor device according to claim 1, wherein the device is a MOSFET or IGBT.

14. A method for forming a semiconductor device with active and termination regions formed in a semiconductor substrate having an upper surface, a termination including a trench extending into the substrate from said upper surface within said termination region, wherein said termination trench is at least partly filled with an insulating material which extends from the termination trench to overlie adjacent regions of the device above said surface, and wherein a channel stop region extends laterally from a side wall of the termination trench into the substrate, the method comprising providing a semiconductor substrate of a first conductivity type and having an upper surface, forming a termination trench in the surface of said substrate in said termination region, and introducing a dopant into said substrate through at least a portion of a side wall of said termination trench to form said channel stop region.

15. A method according to claim 14, wherein a masking layer is provided on said upper surface of the substrate to define the location of said termination trench inner trench sidewall.

16. A method according to claim 15, wherein said masking layer subsequently prevents dopant used to form the channel stop region from entering the substrate through said upper surface.

17. A method according to claim 16, wherein said masking layer is an oxide layer.

18. A method according to claim 17, wherein said masking layer includes a layer of field oxide located between termination and active regions of the device.

19. A method according to claim 14, further comprising the formation of an active trench within said active region simultaneously with the formation of said termination trench.

20. A method according to claim 19, wherein said masking layer defines the positions of both termination and active trenches.

21. A method according to claim 19, further comprising forming a insulation layer in the active and termination trenches and depositing a conductive material within said trenches over the insulation layer, and providing said gate material to a level below said upper surface, leaving at least upper portions of a side wall of the termination trench free of said conductive material for subsequent introduction of said channel region dopant.

22. A method according to claim 21, wherein the conductive material initially fills the trenches and is then etched back within the active and termination trenches to below the level of said upper surface of the substrate.

23. A method according to claim 14, wherein subsequent to formation of said channel stop region an insulating material is deposited to fill at least said termination trench.

24. A method according to claim 14, wherein the channel stop regions are formed simultaneously with the formation of source regions within the active region of the device by a single doping operation.

25. A semiconductor device, comprising active and termination regions formed in a semiconductor substrate having an upper surface, a termination including a trench extending into the substrate from said upper surface within said termination region:

wherein said termination trench is at least partly filled with an insulating material which extends from the termination trench to overlie adjacent regions of the device above said surface, and wherein a channel stop region extends laterally from a side wall of the termination trench into the substrate;

wherein an oxide layer is supported on the upper surface of said substrate adjacent opposing sides of said termination trench, and said insulating material extends from said termination trench to overlie said oxide layer; and

wherein said active region comprises at least one trench extending from said upper surface immediately adjacent a body region of a second conductivity type formed below said surface, and a region of substantially the same composition as the channel stop region extending laterally from the active trench into the body region.

26. A semiconductor device according to claim 25, wherein said active trench is a gate trench substantially filled with a gate material isolated from the substrate and body regions by a thin layer of gate insulator.

27. A semiconductor device according to claim 26, wherein said termination trench is at least partially lined with a layer of said gate insulator material.

28. A semiconductor device according to claim 27, wherein a lower portion of said termination trench is filled with gate material, said isolation material overlying said gate material within said termination trench.

29. A semiconductor device according to claim 28, wherein the termination trench is of similar width or narrower than the gate trench.

30. A semiconductor device according to claim 27, wherein at most only a small amount of said gate material is present in the termination trench underlying said isolation material.

31. A semiconductor device according to claim 30, wherein there is no gate material present within the termination trench.

32. A semiconductor device according to claim 30 or claim 31, wherein the termination trench is wider than said gate trench.