Self-coplanarity bumping shape for flip chip

• US 6,940,178 B2
• Filed: 02/22/2002
• Issued: 09/06/2005
• Est. Priority Date: 02/27/2001
• Status: Active Grant

• Current Assignee: Stats Chippac Incorporated (JCET Group Co., Ltd.)
• Original Assignee: Chippac Company Limited
• Inventors: Kweon, Young-Do, Kim, Kyung-Moon, Pendse, Rajendra, Ahmad, Nazir
• Primary Examiner(s): Thai, Luan
• Application Number:
  US10/080,384
• Publication Number:
  US 20020151228A1
• Time in Patent Office: 1,292 Days
• Field of Search: 257/780, 257737-738, 257778-779
• US Class Current: 257/780
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/11831 involving a chemical process, e.g. etching the bump connector
• CPC Class Codes: H01L 2224/1184 involving a mechanical process, e.g. planarising the bump connector
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/14 of a plurality of bump connectors
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A stud bump structure for electrical interconnection between a pair of members includes a base portion, and a stem portion. The base portion is affixed to a pad or trace in one of the pair of members to be interconnected (such as an integrated circuit chip), and the stem end is configured to contact a metal pad on the other member (such as a printed circuit board) to complete the interconnect. According to the invention, the stem end is truncated to form a transverse plane, and the stem is more compliant than the base. Also, a method for forming a stud bump on a contact surface, includes forming a bump base portion on the surface, drawing out a generally conical tail from a top of the base, and truncating the tail to form a stem portion having a planar transverse top surface and having a length from the top of the base portion to the top surface. In some embodiments the tail portion, at least, of the stud bump is formed using a wire bonding tool. Also, a method for forming an interconnect between a first member and a second member of an electronic package includes providing one of the members with the stud bumps of the invention and then bringing the corresponding bumps and pads together in a bonding process, the compliance of the stems portions of the bumps accommodating the variance from coplanarity of the pad surfaces.

Claims

1. A stud bump structure, comprising:

a based portion, affixed to a first member of an interconnect pair, and

a stem portion, wherein the stem portion has a transverse planar top surface configured to contact a metal pad on a second member of the interconnect pair, and wherein the stem portion is more compliant than the base portion,

the base portion comprising a first material and the stem portion comprising a second material, the second material being more compliant than the first material,

wherein the first material is selected from the group consisting of nickel, copper, nickel alloys and copper alloys.

2. The stud bump structure of claim 1 wherein the second material is selected from the group consisting of a solder, gold, and gold alloys.

3. The stud bump structure of claim 1 wherein at least the top surface of the stem has a smaller diameter than the base.

4. The stud bump structure of claim 1 wherein the stud bump stem height is greater than the maximum range of noncoplanarity of all the pads on the second member.

5. The stud bump structure of claim 1 wherein the bump base portion comprises a material having a similar compliance characteristic as the material of the stem, and wherein at least the top surface of the stem has a smaller diameter than the base.

6. The stud bump structure of claim 5 wherein the bump base portion comprises a material having the same compliance characteristic as the material of the stem.

7. The stud bump structure of claim 5 wherein the stud bump stem height is greater than the maximum range of noncoplanarity of all the pads on the second member.

8. The stud bump structure of claim 1 wherein the bump base portion comprises the same material as the stem portion.

9. The stud bump structure of claim 1 wherein at least one of the bump base portion and the bump stem portion comprises gold or a gold alloy.

10. The stud bump structure of claim 1 wherein the base portion is affixed to a conductive site exposed in an opening in a passivation material, and wherein a diameter of the base portion is less than 0.85 times a diameter of the opening in the passivation material.

11. A stud bump structure, comprising

a base portion, affixed to a first member of an interconnect pair, and

a stem portion, wherein the stem portion has a transverse planar top surface configured to contact a metal pad on a second member of the interconnect pair, and wherein the stem portion is more compliant than the base portion,

the base portion comprising a first material and the stem portion comprising a second material, the second material being more compliant than the first material

wherein the first material comprises copper and the second material comprises gold or a gold alloy.

12. An integrated circuit chip for use in a flip chip package, the chip having a plurality of stud bumps on contact sites at specified locations on a surface thereof, the stud bumps each having a base portion and having a stem portion that is more compliant than the base portion, the stem portion having a transverse planar top surface, the base portion comprising a first material selected from the group consisting of nickel, copper, nickel alloys and copper alloys and the stem portion comprising a second material, the second material being more compliant than the first material.

13. A flip chip semiconductor package, comprising

an integrated circuit chip having a plurality of stud bumps on contact sites at specified locations on a surface thereof, the stud bumps each having a base portion and having a stem portion that is more compliant than the base portion, the stem portion having a transverse planar top surface, the base portion comprising a first material selected from the group consisting of nickel, copper, nickel alloys and copper alloys and the stem portion comprising a second material, the second material being more compliant than the first material;

and

a substrate having a plurality of bonding pads at specified locations on a surface of thereof, the respective specified locations on the integrated circuit chip and the substrate corresponding, the stem portions of the stud bumps on the chip being in electrical contact with the corresponding pads on the substrate.