PWM-based DC-DC converter with assured dead time control exhibiting no shoot-through current and independent of type of FET used

• US 6,940,262 B2
• Filed: 12/02/2003
• Issued: 09/06/2005
• Est. Priority Date: 12/31/2002
• Status: Active Grant

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Inventors: Sferrazza, Paul K., Dequina, Noel, Preslar, Donald R.
• Primary Examiner(s): Laxton, Gary L
• Application Number:
  US10/725,764
• Publication Number:
  US 20040130307A1
• Time in Patent Office: 644 Days
• Field of Search: 323/224, 323/282, 323/284, 323/285, 327/108, 327/112, 327/389, 327/394, 327/398, 327/399
• US Class Current: 323/284
• CPC Class Codes: H02M 1/38 Means for preventing simultaneous conduction of switches
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A control circuit for a switch mode DC-DC converter contains an arrangement of monitored LGATE, UGATE and PHASE node condition threshold detectors, outputs of which are processed in accordance with a switching control operator to ensure that each of an upper FET (UFET) and a lower FET (LFET) is completely turned off before the other FET begins conduction, thereby maintaining a dead time that exhibits no shoot-through current and is independent of the type of switching FET.

Claims

1. A control circuit for a switch mode DC-DC converter comprising an arrangement of LGATE, UGATE and PHASE node condition threshold detectors, said LGATE condition threshold detector being operative to monitor the gate (LGATE) of a lower FET (LFET), said UGATE condition threshold detector being operative to monitor the gate (UGATE) of an upper FET (UFET), and said PHASE node condition threshold detector being operative to monitor a phase node voltage at a PHASE node or common node between said UFET and said LFET, voltage outputs of said threshold detectors being processed in accordance with a switching control operator to ensure that each of said UFET and said LFET is completely turned off before the other FET begins conduction, thereby maintaining a dead time that exhibits no shoot-through current and is independent of type of switching FET, and wherein said switching control operator is operative to trigger turn-on of said UFET, which causes the phase node voltage to increase from a first voltage level to a second voltage level higher than said first voltage level, in response to turn-off of said LFET, and in response to said phase node voltage at said PHASE node having reached a prescribed negative polarity voltage threshold following a predetermined blanking delay subsequent to said turn-off of said LFET.

2. The control circuit according to claim 1, wherein said switching control operator is operatives, in response to said PHASE node not having reached said prescribed negative polarity voltage following said predetermined blanking delay subsequent to turn-off of said LFET, to monitor whether said phase node voltage has increased from said first voltage level to a prescribed positive polarity voltage threshold and, in response to said phase node voltage having increased from said first voltage level to said prescribed positive polarity voltage threshold, said switching control operator is operative to trigger turn-on of said UFET, and thereby causing said phase node voltage to increase to said second voltage level.

3. The control circuit according to claim 2, wherein said switching control operator is operative, in response to an elapse of a prescribed time-out without either of said prescribed positive and negative polarity voltage thresholds having been reached at said phase node following said blanking delay, to trigger turn-on of said LFET, causing said phase node voltage to increase from said first voltage level to said second voltage level.

4. The control circuit according to claim 1, wherein said switching control operator is operative, in response to turn-off of said UFET, and in response to a UGATE voltage at said UGATE dropping to a voltage level that is a prescribed value above said phase node voltage, to trigger a prescribed time out and then turn on said LFET in response to expiration of said prescribed time out.

5. The control circuit according to claim 1, wherein said switching control operator is operative, in response to turn-off of said UFET, and in response to said phase node voltage reaching a predetermined threshold voltage, to turn on said LFET.

6. A method for controlling a switch mode DC-DC converter comprising an upper FET (UFET), having an upper gate (UGATE), and a lowar FET (LFET) having a lower gate (LGATE), said UFET and said LFET being coupled between power supply voltage rails, and having a common node or PHASE node therebetween, said method comprising the steps of:

(a) monitoring an LGATE voltage, a UGATE voltage and a phase node voltage; and

(b) in response to turn-off of said LFET, and in response to said phase node voltage at said PHASE node having reached a prescribed negative polarity voltage threshold following a predetermined blanking delay subsequent to said turn-off of said LFET, triggering turn-on of said UFET, thereby causing said phase node voltage to increase from a first voltage level to a second voltage level higher than said first voltage level.

7. The method according to claim 6, wherein step (b) further comprises, in response to said PHASE node not having reached said prescribed negative polarity voltage following said predetermined blanking delay subsequent to turn-off of said LFET, monitoring whether said phase node voltage has increased from said first voltage level to a prescribed positive polarity voltage threshold and, in response to said phase node voltage having increased from said first voltage level to said prescribed positive polarity voltage threshold, triggering turn-on of said UFET, thereby causing said phase node voltage to increase to said second voltage level.

8. The method circuit according to claim 7, wherein step (b) further comprises, in response to an elapse of a prescribed time-out without either of said prescribed positive and negative polarity voltage thresholds having been reached at said phase node following said blanking delay, triggering turn-on of said UFET, thereby causing said phase node voltage to increase from said first voltage level to said second voltage level.