Circuitry to reduce PLL lock acquisition time

• US 6,940,356 B2
• Filed: 02/17/2004
• Issued: 09/06/2005
• Est. Priority Date: 02/14/2003
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Hulfachor, Ronald B., McDonald, James J. II
• Primary Examiner(s): NGUYEN, LINH M
• Application Number:
  US10/780,493
• Publication Number:
  US 20040160281A1
• Time in Patent Office: 567 Days
• Field of Search: 331/14, 331/16, 331/17, 331/25, 331/175, 331/DIG.2, 327/148, 327/157, 327/146, 327/155, 327/156, 375/375, 375/376, 375/373
• US Class Current: 331/16
• CPC Class Codes: H03L 7/0898 the source or sink current values being variable H03L7/0896 takes precedence
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: H03L 7/1075 by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth H03L7/1072 takes precedence
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: Y10S 331/02 Phase locked loop having lock indicating or detecting means

Abstract

A phase locked loop, PLL, is described with multiple parallel charge pumps that are selectively disabled as phase lock is approached. A lock detection circuit is described that enabled reference currents to be fed to the parallel charge pumps. The error signal from a phase detector is arranged as UP and a DOWN signals that are averaged in the lock detector. When the average error is large, all the reference currents feed the charge pumps that provide a high loop gain to reduce the lock time. As the lock becomes closer selective reference currents are disabled to reduce loop gain so that a smooth transition to lock is made. Selectively switching currents into a low pass filter that usually follows a charge pump in a PLL circuit automatically reduces switching noise by the operation of the low pass filter.

Claims

1. A phase locked loop (PLL) circuit comprising:

a phase detector comparing an input signal to a feedback signal, the phase detector providing an error signal,

a low pass filter defining a filter output,

a voltage controlled oscillator accepting the output from the low pass filter and output the feedback signal,

at least two charge pumps that each a driving signal to the low pass filter,

wherein the driving signal is responsive to the error signal,

a lock detector that accepts the error signal and in response outputs at least one lock signal, wherein the one lock signal represents an indication of a coarse lock,

a reference generator that accepts the lock signal and in response outputs one reference signal to one charge pump, wherein the reference signal controls the charge pump, and

wherein when the at least two charge pumps provide a signal to the low pass filter the PLL loop bandwidth is higher than when one of the at least two charge pump is inactive.

2. The phase locked loop circuit of claim 1 wherein the at least two charge pumps are each arranged to accept a reference current and output a current to the low pass filter.

3. The phase locked loop circuit of claim 2 wherein the at least two charge pumps are each arranged to accept the same reference current but output different currents to the low pass filter.

4. The phase locked loop circuit of claim 2 wherein the at least two charge pumps are each arranged to accept different reference currents and output different currents to the low pass filter.

5. The phase locked loop circuit of claim 4 wherein the reference source comprises a a first reference current source driving one charge pump, and a second reference current source driving a second charge pump, and wherein the second reference current source is larger than the first reference current source.

6. The phase locked loop of claim 5 wherein the second current source is selected on or off by the coarse lock signal from the lock detector.

7. The phase locked loop of claim 1 wherein the first lock signal is latched.

8. The phase locked loop of claim 1 wherein the reference generator comprises:

first, second and third reference current sources, where the first reference current source has lower magnitude than the second reference current source which has a lower magnitude than the third reference current source, and wherein the lock detector comprises at least two lock signals, a coarse lock signal that controls the third reference current source, and a second lock signal that controls the second reference current source.

9. The phase locked loop of claim 1 wherein the lock detector comprises:

at least one comparator,

a circuit that averages the error signal, the averaged error signal connects to an input of the at least one comparator,

a voltage divider circuit arranged to provide a different trigger voltage to the second input of the at least one comparator, wherein when the average error signal reaches the trigger voltage of each comparator, the lock signal disables the corresponding reference current source, thereby reducing the loop gain of the phase locked loop.

10. A phase locked loop that includes a phase detector providing an error signal to a charge pump, wherein the charge pump in response outputs a current into a low pass filter that outputs a signal to a voltage controlled oscillator, whose output is divided thereby producing a feedback signal that is compared to an input signal in the phase detector, further comprising a lock detector that provides a coarse lock signal indicating that a coarse lock state has been reached for the PLL, and at least one additional charge pump that defines an output current into the low pass filter, the additional charge pump accepts and is controlled on or off by the coarse lock signal, wherein when the additional charge pump is off the loop bandwidth of the phase locked loop is lowered.

11. The phase locked loop of claim 10 further comprising additional charge pumps and lock detectors that output additional corresponding lock signals to the additional charge pumps, the additional lock signals indicating finer and finer lock conditions of the phase locked loop, wherein as the phase locked loop approaches closer to the finest lock condition, the additional lock signals incrementally turn off the corresponding charge pumps to incrementally reduce the phase locked loop bandwidth.

12. The phase locked loop of claim 10 further comprising a reference current arranged to accept the coarse lock signal and provide a reference current to the charge pump that controls the charge pump output current, wherein when the coarse lock signal is not asserted the reference current drives the charge pump to output a current to the low pass filter, and when the coarse lock signal is asserted turning off the reference current that in turn turns off the charge pump current to the low pass filter.

13. A method of operating a phase locked loop, wherein the loop contains a low pass filter with an output driving a voltage controlled oscillator that outputs a signal that is divided forming a feedback and fed back to a phase detector that compares the feedback signal to an input signal, the phase detector outputting an error signal, wherein the error signal ultimately drives a current via multiple charge pumps into the low pass filter, the method comprising the steps of:

comparing the error signal to reference levels, wherein the reference levels indicate degrees of coarser and finer lock states of the phase locked loop, wherein, in response to the error signal reaches the corresponding reference level,

adjusting the current from the charge pumps so that the loop gain of the phase locked loop is reduced as finer locks are reached.