Switch architecture using MEMS switches and solid state switches in parallel

• US 6,940,363 B2
• Filed: 12/17/2002
• Issued: 09/06/2005
• Est. Priority Date: 12/17/2002
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ma, Qing, Zipper, Eliav
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): TAKAOKA, DEAN O
• Application Number:
  US10/322,290
• Publication Number:
  US 20040113713A1
• Time in Patent Office: 994 Days
• Field of Search: 333/101, 333/103, 333/262, 333/105
• US Class Current: 333/103
• CPC Class Codes: H01H 1/0036 Switches making use of microelectromechanical systems [MEMS] for electromagnetic relays H01H50/005; for electrostatic relays H01H59/0009
• CPC Class Codes: H01H 59/0009 making use of micromechanics
• CPC Class Codes: H01H 9/541 Contacts shunted by semiconductor devices
• CPC Class Codes: H01H 9/542 Contacts shunted by static switch means

Abstract

In a switching scheme mechanical MEMs switches are connected in parallel with solid state switches. This parallel MEMS/solid-state switch arrangement takes advantage of the fast switching speeds of the solid state switches as well advantage of the improved insertion loss and isolation characteristics of the MEMS switches. The solid-state switches only need to be energized during a ramp up/down period associated with the slower MEMs switch thus conserving power. As an additional advantage, using a solid-state switch in parallel with MEMs switches improves the transient spectrum of the system during switching operations.

Claims

1. A switch circuit, comprising:

a first contact to connect to a first electrical device;

a second contact to connect to a second electrical device;

a solid-state switch connected between said first contact and said second contact;

a mechanical switch connected between said first contact and said second contact in parallel combination with said solid-state switch, said mechanical switch having a slower switching speed than said solid-state switch and having a ramp-up period when turned on and a ramp-down period when turned off; and

a control sequence to turn on said solid-state switch during said ramp-up period and said ramp-down period.

2. The switch circuit as recited in claim 1, wherein said mechanical switch comprises:

an array of mechanical switches connected between said first contact and said second contact.

3. The switch circuit as recited in claim 1, further comprising:

a shunt circuit between said second contact and ground, said shunt circuit comprising;

a solid state switch; and

a mechanical switch connected in parallel combination with said solid state switch.

4. The switch circuit as recited in claim 1 wherein said mechanical switch is a micro-electromechanical system (MEMs) switch.

8. The switch for a communication system as recited in claim 4 wherein said mechanical switches comprise micro-electromechanical system (MEMs) switches.

5. A switch for a communication device, comprising:

an antenna;

a receiver;

a transmitter;

a first switch circuit to connect said antenna to said receiver, said first switch circuit comprising;

a solid-state switch; and

a mechanical switch connected in parallel combination with said solid-state switch;

a second switch circuit to connect said antenna to said transmitter, said second switch circuit comprising;

a solid state switch; and

an array of mechanical switches connected in parallel with said solid state switch.

6. The switch for a communication device as recited in claim 5, further comprising:

a receiver shunt circuit comprising a solid-state switch in parallel connection with a mechanical switch to shunt said receiver to ground when said first switch circuit is in an off state.

7. The switch for a communication device as recited in claim 6, further comprising:

a transmitter shunt circuit comprising a solid-state switch in parallel connection with a mechanical switch to shunt said transmitter to ground when said second switch circuit is in an off state.

9. A method for switching, comprising:

providing a first switch between two electrical devices;

providing a second switch in parallel with said first switch, said second switch being faster than said first switch, said first switch having a ramp-up period when turned on and a ramp down period when turned off;

turning on said first switch; and

turning on said second switch during said ramp-up period and turning off said second switch after said ramp-up period;

turning off said first switch;

turning on said second switch during said ramp down period and turning off said second switch after said ramp-down period.

10. The method as recited in claim 9, further comprising:

providing a first isolation switch;

providing a second isolation switch in parallel with said first isolation switch, said second isolation switch being faster than said first isolation switch, said first isolation switch having a ramp-up period when turned on;

turning on said first isolation switch and said second isolation switch when said first switch and said second switch are turned off; and

turning off said second isolation switch after said ramp-up period of said first isolation switch.

11. The method as recited in claim 9, wherein said first switch comprises a micro-electromechanical system (MEMs) switch and said second switch comprises a solid-state switch.

12. The method as recited in claim 10, wherein said first isolation switch comprises a micro-electromechanical system (MEMs) switch and said second isolation switch comprises a solid-state switch.

13. The method as recited in claim 11, wherein said second switch comprises an array of second switches.