Active pixel sensor with noise cancellation

• US 6,940,551 B2
• Filed: 09/24/2001
• Issued: 09/06/2005
• Est. Priority Date: 09/25/2000
• Status: Expired due to Fees

• Current Assignee: Foveon, Inc. (Avis Budget Group Incorporated)
• Original Assignee: Foveon, Inc. (Avis Budget Group Incorporated)
• Inventors: Merrill, Richard B.
• Primary Examiner(s): HO, TUAN V
• Application Number:
  US09/963,027
• Publication Number:
  US 20020036700A1
• Time in Patent Office: 1,443 Days
• Field of Search: 348/294, 348/300, 348/301, 348/302, 348/308, 348/333.01, 348/241, 348/243, 348/248, 250/208.1, 257/72, 257/361, 257/362, 257/223, 257/229, 257/230
• US Class Current: 348/301
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS

Abstract

A CMOS active pixel sensor with noise reduction employs a photodetector. A reset switch is coupled between a reset potential line and the photodetector and is controlled by a reset line. An amplifier is coupled to the photodetector. A kTC noise reducing circuit is disposed within the pixel sensor. A readout circuit is coupled to the kTC noise reducing circuit and is controlled by a row-select line.

Claims

1. An active pixel sensor comprising:

a photodetector;

a reset switch coupled between a reset potential line and said photodetector and controlled by a reset signal line;

an amplifier coupled to said photodetector;

a kTC noise cancellation circuit disposed within the pixel sensor;

a readout circuit coupled to said kTC noise cancellation circuit and controlled by a row-select line.

2. An active pixel sensor disposed on a substrate, comprising:

a photodetector

a first reset transistor having a drain coupled to a first reset potential, a gate coupled to a first reset signal line, and a source coupled to said photodetector;

a first source-follower amplifier transistor having a drain coupled to a first source-follower drain potential, a gate coupled to said photodetector, and a source;

a bias transistor having a drain coupled to said source of said source-follower amplifier transistor, a gate coupled to a bias potential, and a source coupled to a fixed potential;

a capacitor having a first terminal coupled to said source of said first source-follower amplifier transistor and a second terminal;

a second reset transistor having a drain coupled to a second reset potential, a gate coupled to a second reset signal line, and a source coupled to said gate terminal of said capacitor;

a second source-follower amplifier transistor having a drain coupled to a second source-follower drain potential, a gate coupled to said gate terminal of said capacitor, and a source; and

a row-select transistor having a drain coupled to the source of said second source-follower amplifier transistor, a gate coupled to a row-select line, and a source coupled to a column output line.

3. The active pixel sensor of claim 2 wherein said source of said reset transistor and said gate of said first source-follower amplifier transistor are coupled to said photodetector through a barrier transistor having a gate coupled to a barrier potential.

4. The active pixel sensor of claim 2, wherein said capacitor is a MOS capacitor.

5. The active pixel sensor of claim 2, wherein said capacitor is an embedded DRAM capacitor.

6. The active pixel sensor of claim 5, wherein said second terminal of said DRAM capacitor has less stray capacitance to substrate than said first terminal.

7. A method for reducing kTC noise in a CMOS active pixel sensor comprising:

applying a reset potential to a photodetector within the active pixel sensor;

storing a noise component of said reset potential within said active pixel sensor;

integrating photogenerated charge on said photodetector for an integration period to generate a photosignal; and

subtracting said noise component from said photosignal within said active pixel sensor.

8. An active pixel sensor comprising:

a photodetector;

an amplifier having an input and an output;

a reset switch coupled between a reset potential line and said photodetector and controlled by a reset signal line;

a transfer switch coupled between said photodetector and said input of said amplifier and controlled by a transfer signal line;

a DRAM capacitor coupled between said input of said amplifier and a fixed potential;

a row-select switch coupled to said output of said amplifier and controlled by a row-select line.

9. An array of active pixel sensors arranged in rows and columns on a semiconductor substrate comprising:

a reset signal line;

a row-select signal line associated with each row of said array;

an column output line associated with each column of said array;

a plurality of CMOS active pixel sensors, each CMOS active pixel sensor associated with one row and one column of said array and including;

a photodetector;

a reset switch coupled between a reset potential line and said photodetector and controlled by said reset signal line;

an amplifier coupled to said photodetector;

a kTC noise cancellation circuit disposed within the pixel sensor;

a readout circuit coupled to said photodetector and said kTC noise cancellation circuit and to the one of said output signal lines with which it is associated and controlled by the one of said row-select lines with which it is associated.

10. An array of active pixel sensors arranged in rows and columns on a semiconductor substrate comprising:

a first reset signal line;

a second reset signal line;

a row-select signal line associated with each row of said array;

an column output line associated with each column of said array;

a plurality of active pixel sensors, each active pixel sensor associated with one row and one column of said array and including;

a photodetector

a first reset transistor having a drain coupled to a first reset potential, a gate coupled to said first reset signal line, and a source coupled to said photodetector through a barrier transistor having a gate coupled to a barrier potential;

a first source-follower amplifier transistor having a drain coupled to a first source-follower drain potential, a gate coupled to said source of said first reset transistor, and a source;

a bias transistor having a drain coupled to said source of said source-follower amplifier transistor, a gate coupled to a bias potential, and a source coupled to a fixed potential;

a MOS capacitor having a substrate terminal coupled to said source of said first source-follower amplifier transistor and a gate terminal;

a second reset transistor having a drain coupled to a second reset potential, a gate coupled to said second reset signal line, and a source coupled to said gate terminal of said MOS capacitor;

a second source-follower amplifier transistor having a drain coupled to a second source-follower drain potential, a gate coupled to said gate terminal of said MOS capacitor, and a source; and

a row-select transistor having a drain coupled to the source of said second source-follower amplifier transistor, a gate coupled to the row-select line with which it is associated, and a source coupled to the column output line with which it is associated.

11. The array of claim 10, wherein each said MOS capacitor is an embedded DRAM capacitor.