Semiconductor memory devices for outputting bit cell data without separate reference voltage generator and related methods of outputting bit cell data

• US 6,940,743 B2
• Filed: 06/09/2004
• Issued: 09/06/2005
• Est. Priority Date: 06/11/2003
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jung, Jong-hoon
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US10/864,276
• Publication Number:
  US 20050018470A1
• Time in Patent Office: 454 Days
• Field of Search: 365/145, 365/149, 365/207, 365/210
• US Class Current: 365/145
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4099 Dummy cell treatment; Reference voltage generators
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

Semiconductor memory devices are provided which include an array of memory cells, an array of reference cells, and a plurality of sense amplifiers that are associated with respective of the memory cells. The reference cells have a first capacitor that is coupled to a first supply voltage, to a first complementary bit line associated with one of the memory cells and to a second complementary bit line that is associated with a different memory cell. The sense amplifiers are configured to sense and amplify the voltage difference between a signal on the first bit line and a signal on the first complementary bit line. These semiconductor memory devices may output bit cell data without a separate reference voltage generator.

Claims

1. A semiconductor memory device, comprising:

a memory cell array having at least first and second memory cells and at least one word line, the first memory cell having an associated first bit line and an associated first complementary bit line and the second memory cell having an associated second bit line and an associated second complementary bit line;

a reference cell array having an associated reference word line and a reference cell, wherein the reference cell includes a first capacitor that is coupled to a first supply voltage, a first transistor having a control terminal that is coupled to the reference word line and a second transistor having a control terminal that is coupled to the reference word line, wherein the first capacitor is coupled to the first complementary bit line through the first transistor and that is coupled to the second complimentary bit line through the second transistor; and

at least one sense amplifier that is associated with the first memory cell and that is configured to sense and amplify the voltage difference between a signal on the first bit line and a signal on the first complementary bit line.

2. The semiconductor memory device of claim 1, wherein the signal on the first bit line comprises a data signal output from the first memory cell and wherein the signal on the first complementary bit line comprises a signal output from the reference cell.

3. The semiconductor device of claim 2, wherein the reference cell supplies a reference cell voltage to both the first and second memory cells.

4. The semiconductor memory device of claim 1, wherein a reference cell voltage signal is output from the first capacitor to the first complementary bit line in response to the activation of a reference word line signal that turns on the first and second transistors.

5. The semiconductor memory device of claim 4, wherein a pulse width of an activated word line signal that is carried by the word line associated with the first memory cell is greater than a pulse width of the activated reference word line signal.

6. The semiconductor memory device of claim 1, wherein the first bit line and the first complementary bit line are precharged to a second supply voltage that is different than the first supply voltage.

7. The semiconductor memory device of claim 4, wherein the reference cell further comprises a third transistor coupled between the first supply voltage and the first capacitor, wherein the third transistor is turned on in response to activation of a ready signal to charge the first capacitor to the first supply voltage.

8. The semiconductor memory device of claim 1, wherein the reference cell further comprises a third transistor and a second capacitor, wherein the second capacitor is coupled to the first complementary bit line through the third transistor and the first transistor and is coupled to the second complimentary bit line through the second transistor, and wherein the second capacitor is coupled to a second supply voltage.

9. The semiconductor memory device of claim 8, wherein a reference cell voltage is stored in the first and second capacitors in response to a signal that turns on the third transistor to cause charge-sharing between the first and second capacitors.

10. The semiconductor memory device of claim 9, wherein the reference cell further comprises a fourth transistor coupled between the first capacitor and the first supply voltage and a fifth transistor coupled between the second capacitor and the second supply voltage.

11. A method of reading a data bit from a memory cell in a memory cell array, the memory cell array further comprising a bit line, a complementary bit line and a word line that are associated with the memory cell, the method comprising:

precharging the bit line and the complementary bit line to a first supply voltage;

storing a second supply voltage in a reference cell that is associated with the memory cell;

outputting a reference signal having a voltage between the first supply voltage and the second supply voltage from the reference cell to the complementary bit line through a first transistor that is activated by activation of a reference word line signal and outputting the reference signal from the reference cell to a second complimentary bit line through a second transistor that is activated by activation of the reference word line signal; and

sensing and amplifying the voltage difference between the bit line and the complementary bit line to output the data bit from the memory cell.

12. The method of claim 11, wherein the reference signal has a voltage equal to approximately one-half the second supply voltage.

13. The method of claim 11, further comprising storing the reference signal having a voltage between the first supply voltage and the second supply voltage in a first capacitor prior to outputting the reference signal to the complimentary bit line and to the second complimentary bit line.

14. The method of claim 11, wherein storing the second supply voltage in the reference cell that is associated with the memory cell comprises storing the second supply voltage in a first capacitor of the reference cell in response to activation of a ready signal.

15. The method of claim 11, wherein the second supply voltage is stored in a first capacitor in the reference cell and further comprising storing the first supply voltage in a second capacitor included in the reference cell.

16. The method of claim 15, further comprising storing a reference cell voltage in at least one of the first and second capacitors by sharing charge between the first and second capacitors.

17. The method of claim 16, wherein the reference cell voltage stored in the at least one of the first and second capacitors is in between the first supply voltage and the second supply voltage.

18. The method of claim 14, further comprising outputting a second reference signal from the reference cell that is in between the first supply voltage and a second supply voltage to a complementary bit line associated with a second memory cell.

19. A semiconductor memory device which outputs bit cell data in a read operation, comprising:

a bit cell array which stores the bit cell data in a plurality of bit cells, each bit cell defined by intersection of a plurality of bit lines, a plurality of complementary bit lines and a plurality of word lines, the bit cell array outputting a bit cell signal, read from a bit cell in the plurality of bit cells that is defined by an activated word line signal, a selected bit line and a selected complementary bit line, to the selected first bit line;

a reference cell array having a plurality of reference cells that each store a reference cell voltage, wherein the reference cell associated with the bit cell defined by the activated word line signal, the selected bit line and the selected complementary bit line includes a first capacitor that is coupled to a first supply voltage, to the selected complementary bit line through a first transistor having a control terminal that is coupled to a reference word line signal and to a second complementary bit line through a second transistor having a control terminal that is coupled to the reference word line signal; and

a sense amplifying unit, which senses the bit cell signal output to the selected bit line and a reference signal output to the selected complementary bit line from the reference cell associated with the bit cell defined by the activated word line signal, the selected bit line and the selected complementary bit line amplifies a voltage difference between the bit cell signal and the reference signal, and outputs the amplified voltage difference.

20. The semiconductor memory device of claim 19, wherein the reference signal provided to the complimentary bit line and to the second complimentary bit line is the charge stored in the first capacitor shared between the complimentary bit line and the second complimentary bit line.

21. The semiconductor memory device of claim 19, wherein a pulse width of the activated reference word line signal is smaller than a pulse width of the activated word line signal.

22. The semiconductor memory device of claim 19, wherein the reference cell associated with the bit cell defined by the activated word line signal, the selected bit line and the selected complementary bit line further comprises a third transistor and a second capacitor, wherein the second capacitor is coupled to the first complementary bit line through the third transistor and the first transistor and is coupled to the second complimentary bit line through the second transistor, and wherein the second capacitor is coupled to a second supply voltage.

23. A method of reading bit cell data from a semiconductor memory device, the method comprising:

storing the bit cell data in a bit cell having an associated bit line, an associated complementary bit line and an associated word line;

storing a first supply voltage in a first capacitor of a reference cell associated with the bit cell in response to activation of a ready signal;

storing a second supply voltage in a second capacitor of the reference cell associated with the bit cell in response to activation of the ready signal;

activating a first transistor coupled between the first capacitor and the second capacitor to store a reference cell voltage having a value between the first supply voltage and the second supply voltage in each of the first and second capacitors;

outputting a bit cell signal which is read from the bit cell to the bit line;

outputting a reference signal from the reference cell to the complementary bit line and to a second complementary bit line associated with a second bit cell;

sensing the bit cell signal output to the bit line and the reference signal output to the complementary bit line;

amplifying a voltage difference between the bit cell signal and the reference signal; and

outputting the amplified voltage difference.

24. The method of claim 23, wherein the bit line and the complementary bit line are precharged to a first supply voltage prior to the read operation.