Highly compact non-volatile memory and method therefor with space-efficient data registers

• US 6,940,753 B2
• Filed: 09/24/2002
• Issued: 09/06/2005
• Est. Priority Date: 09/24/2002
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Cernea, Raul-Adrian
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): HUR, JUNG H
• Application Number:
  US10/254,221
• Publication Number:
  US 20040057282A1
• Time in Patent Office: 1,078 Days
• Field of Search: 365/185.01, 365/185.21, 365/185.08, 365/189.08, 365/189.12, 365/189.05, 365/221
• US Class Current: 365/185.08
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 19/00 Digital stores in which the information is moved stepwise, e.g. shift registers
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output
• CPC Class Codes: G11C 7/1036 using data shift registers

Abstract

A non-volatile memory device capable of reading and writing a large number of memory cells in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. In one aspect, data latches associated with the multiple read/write circuits are I/O enabled and coupled in a compact manner for storage and serial transfer. They are implemented by one or more chain of link modules, which can selectively behave as inverters or latches. A method enables the use of a minimum number of link modules by cycling data between a set of master link modules and a substantially smaller set of slave link modules.

Claims

1. A method of storing N data items in a chain of link modules in a non-volatile memory device, comprising:

(a) providing a chain including at least N link modules, wherein each module is controllable to behave either as an inverter or as a latch;

(b) inputting said N data items serially to said chain from an opposite end to a first link module;

(c) latching a first data item into said first master link module while controlling said first link module to behave as a latch and all intervening link modules to behave as inverters;

(d) latching a next data item into a next link module while controlling said next link module to behave as a latch and all intervening link modules to behave as inverters; and

(e) repeating step (d) until all N data items have been moduled in said chain.

4. The method as in any one of claims 1-3, wherein said chain is further partitioned into more than one chain.

2. A method of reading N data items stored in a chain of link modules in a non-volatile memory device, each link module being controllable to behave either as an inverter or a latch, said method comprising:

(a) reading out from said chain beginning from said first link module a first data item stored in said first link module while controlling all link modules to behave as latches;

(b) reading out a next data item stored in a next link module while controlling those link modules that have previously been readout to behave as inverters and those link modules that have not been readout to behave as latches; and

(c) repeating step (b) until all N data items have been readout.

3. The method as in claim 2, further comprising:

selectively inverting individual data items as they are being readout.