Method and apparatus for a X-DSL communication processor

• US 6,940,807 B1
• Filed: 10/26/2000
• Issued: 09/06/2005
• Est. Priority Date: 10/26/1999
• Status: Expired due to Fees

• Current Assignee: Ikanos Communications Incorporated (Qualcomm, Inc.)
• Original Assignee: Velocity Communication Incorporated
• Inventors: Heidari, Sam, Shridhar, Avadhani, Rezvani, Behrooz, Ramesh, Tiruvur R., Bajwa, Raminder S., Eskandari, Masoud, Massoudi, Firooz, Begur, Sridhar, Sarmaru, Omprakash S.
• Primary Examiner(s): Sam, Phirin
• Application Number:
  US09/699,193
• Time in Patent Office: 1,776 Days
• Field of Search: 370/352, 370/353, 370/354, 370/357, 370/356, 370/359, 370/389, 370/392, 370/395.52, 370/419, 370/420, 370/421, 370/437, 370/465, 370/468, 370/474, 370/476, 370/493, 370/494, 370/495, 370/210, 375/219, 375/220, 375/222, 375/229
• US Class Current: 370/210
• CPC Class Codes: G06F 17/142 Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm
• CPC Class Codes: H04L 27/2628 Inverse Fourier transform modulators, e.g. inverse fast Fourier transform [IFFT] or inverse discrete Fourier transform [IDFT] modulators H04L27/2634 takes precedence
• CPC Class Codes: H04L 27/265 Fourier transform demodulators, e.g. fast Fourier transform [FFT] or discrete Fourier transform [DFT] demodulators H04L27/26524 takes precedence

Abstract

The current invention provides a DSP which accommodates multiple current X-DSL protocols and is further configurable to support future protocols. The DSP is implemented with shared and dedicated hardware components on both the transmit and receive paths. The DSP implements both the discrete Fourier transform (DFT) and inverse discrete Fourier transform (IDFT) portions across a wide range of sample sizes and X-DSL protocols. Multiple channels, each with varying ones of the X-DSL protocols can be handled in the same session. The DSP offers the speed associated with hardware implementation of the transforms and the flexibility of a software only implementation. Traffic flow is regulated in the chip using a packet based schema in which each packet is associated with a specific channel of upstream and downstream data. Header and control information in each packet is used to govern the processing of each packet as it moves along either the transmit path or receive path. The DSP of the current invention may advantageously be utilized in fields other than communications, such as: medical and other imaging, seismic analysis, radar and other military applications, pattern recognition, signal processing etc. The present invention provides a signal processing architecture that supports scalability of CO/DLC/ONU resources, and allows a significantly more flexible hardware response to the evolving X-DSL standards without over committing of hardware resources. As standards evolve hardware may be reconfigured to support the new standards.

Claims

1. A digital signal processor (DSP) for processing a plurality of multi-tone communication channels, and the DSP comprising

a two-dimensional Fourier transform circuit including:

an input memory for storing a succession of two-dimensional sample array having row and column dimensions corresponding with a number of tones in a corresponding one of the plurality of multi-tone communication channels;

row transform components including at least one sliced radix component of order “

R”

performing “

R”

partial row transforms of each successive two-dimensional sample array from the input memory and generating in each partial row transform N/R possible complex outputs, where N corresponds to a number of samples in an associated two-dimensional sample array; and

column transform components with an input coupled to the row transform components to generate complete column transforms from each partial row transform.

2. The digital signal processor of claim 1, wherein the at least one sliced radix component of the row transform components further comprises:

a plurality of sliced radix components equal in a quantity to the order R, and each of the plurality of sliced radix components generating complex outputs from a corresponding unique output node of a radix R butterfly.

3. The digital signal processor of claim 1, wherein the input memory further comprises:

a quantity R of discrete memories each storing a corresponding portion of each two-sample array and each coupled to a corresponding input of the at least one sliced radix component.

4. The digital signal processor of claim 1, further comprising:

a packet based interface for coupling the DSP to a plurality of analog front ends (AFE) each associated with transmission and reception of at least one of the plurality of multi-tone communication channels.

5. The DSP of claim 1, wherein the row transform components and the column transform components of the Fourier transform circuit each include:

at least one corresponding variable radix element with an order of the radix varying in correspondence with dimensions of each two-dimensional sample array.

6. The DSP of claim 1,

wherein the succession of two-dimensional sample arrays stored in the input memory include both two-dimensional sample arrays of time domain samples and two-dimensional sample arrays of frequency domain samples.

7. The DSP of claim 1,

wherein the row and column dimensions of each two-dimensional sample array correspond both with the number of tones together with a domain of the corresponding one of the plurality of multi-tone communication channels.

8. A method for processing a plurality of multi-tone communication channels, comprising:

configuring each sample set of one of frequency domain samples and time domain samples, from each of the plurality of multi-tone communications channels as a two-dimensional array having row and column dimensions corresponding at least with a number of tones in the associated one of the plurality of multi-tone communication channels,

performing a two-dimensional Fourier transform on each two-dimensional array configured in the configuring act, including;

generating sliced radix transforms of an order R for each of N/R selected subsets of each two-dimensional array where N corresponds to a number of samples in an associated two-dimensional array, where each selected subset includes R samples and where each sliced radix transform corresponds with a radix R transformation of R inputs to a selected one among R complex outputs,

completing row and column transforms on the complex outputs generated in the generating act; and

performing the generating and completing acts for remaining ones of the “

R”

complex outputs, to transform each sample set between a corresponding one of a time domain and a frequency domain.

9. The method of claim 8, wherein the performing act further comprises one of the acts of:

repetitively performing the generating and completing acts for remaining ones of the R complex outputs, and

concurrently performing the generating and completing acts for remaining ones of the R complex outputs.

10. The method of claim 8, further comprising:

interfacing with a plurality of analog front ends (AFE) each associated with transmission and reception of at least one of the plurality of multi-tone communication channels subject to the configuring and performing acts.

11. The method of claim 8, wherein the completing act further comprises:

varying an order of a radix to conform with dimensions of each two-dimensional array.

12. The method of claim 8, wherein successive sample sets configured in the configuring act include both upstream and downstream multi-tone communication channels.

13. The method of claim 8, wherein the row and column dimensions of each two-dimensional sample array correspond both with the number of tones together with the domain of the corresponding one of the plurality of multi-tone communication channels.