Programmable analog system architecture

• US 6,941,336 B1
• Filed: 07/18/2001
• Issued: 09/06/2005
• Est. Priority Date: 10/26/2000
• Status: Expired due to Term

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Mar, Monte
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US09/909,047
• Time in Patent Office: 1,511 Days
• Field of Search: 708/3, 708/801
• US Class Current: 708/801
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06G 7/06 Programming arrangements, e.g. plugboard for interconnecting functional units of the computer; Digital programming hybrid computers G06J
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/014 Modifications of generator to ensure starting of oscillations
• CPC Class Codes: H03K 3/02315 Stabilisation of output, e.g. using crystal

Abstract

A programmable analog system architecture and method thereof are described. The analog system architecture and method introduce a single chip solution that contains a set of tailored analog blocks and elements that can be configured and reconfigured in different ways to implement a variety of different analog functions. The architecture includes an array of analog blocks, including continuous time blocks and different types of switched capacitor blocks. The analog blocks can be electrically coupled to each other in different combinations to perform different analog functions. Each analog block includes analog elements that have changeable characteristics that can be specified according to the function to be performed. The architecture thereby facilitates the design of customized chips at less time and expense.

Claims

1. A multi-functional device comprising:

a bus;

a random access memory (RAM) coupled to said bus;

a central processing unit (CPU) coupled to said bus; and

a plurality of analog blocks coupled to said bus, wherein said bus, RAM, CPU and analog blocks reside on a single chip;

said plurality of analog blocks comprising a first set of analog blocks that is selectively and electrically couplable to and decouplable from another analog block in said plurality of analog blocks;

wherein said analog blocks are selectively and electrically coupled to implement a particular analog function, wherein different analog functions are implemented by electrically coupling different combinations of said analog blocks.

2. The multi-functional device of claim 1 wherein said first set of analog blocks comprises switched capacitor blocks.

3. The multi-functional device of claim 1 wherein said first set of analog blocks comprises a first type and a second type, wherein said first type is adapted to receive a first set of inputs and wherein said second type is adapted to receive a second set of inputs different from said first set of inputs.

4. The multi-functional device of claim 1 wherein said plurality of analog blocks also comprises a second set of analog blocks, wherein said second set of analog blocks comprises continuous time blocks.

5. The multi-functional device of claim 1 wherein said plurality of analog blocks is arranged in an array having multiple columns and multiple rows.

6. The multi-functional device of claim 5 wherein said array comprises a first row of continuous time blocks and multiple rows of switched capacitor blocks, wherein said first row is disposed between a row of switched capacitor blocks and an edge of said array.

7. The multi-functional device of claim 5 wherein each analog block in a column is coupled to a respective digital bus.

8. The multi-functional device of claim 1 wherein an analog block comprises a plurality of analog elements having changeable characteristics, wherein a characteristic of an analog element is specified according to said particular analog function.

9. A method for implementing multiple functions in a device, said method comprising:

selecting a first analog block from a plurality of analog blocks coupled to a bus, a random access memory and a central processing unit on a single chip, wherein said first analog block is electrically couplable to and decouplable from another analog block; and

coupling electrically said first analog block to another analog block to implement a first analog function;

wherein different analog functions are implemented by selectively and electrically coupling different combinations of analog blocks.

10. The method of claim 9 wherein said first analog block is a switched capacitor block.

11. The method of claim 9 wherein said plurality of analog blocks comprises a plurality of switched capacitor blocks of a first type and a second type, wherein said first type is adapted to receive a first set of inputs and wherein said second type is adapted to receive a second set of inputs different from said first set.

12. The method of claim 9 wherein said plurality of analog blocks comprises a plurality of continuous time blocks.

13. The method of claim 9 wherein said analog blocks are arranged in an array having multiple columns and multiple rows.

14. The method of claim 13 wherein said array comprises a first row of continuous time blocks and multiple rows of switched capacitor blocks, wherein said first row is disposed between a row of switched capacitor blocks and an edge of said array.

15. The method of claim 13 wherein each analog block in a column is coupled to a respective digital bus.

16. The method of claim 9 comprising:

changing a characteristic of an analog element of said first analog block, wherein said characteristic is specified according to which analog function is being implemented.

17. An array of analog blocks comprising:

a first plurality of analog blocks comprising continuous time blocks; and

a second plurality of analog blocks comprising switched capacitor blocks, said second plurality of analog blocks coupled to said first plurality of analog blocks, wherein a switched capacitor block is selectively and electrically couplable to and decouplable from another analog block;

wherein said first plurality and said second plurality of analog blocks are selectively and electrically coupled in different combinations to implement different analog functions, and wherein said first plurality and second plurality of analog blocks are coupled to a bus, a random access memory and a central processing unit on a single chip.

18. The array of analog blocks of claim 17 wherein said switched capacitor blocks comprise a first type and a second type, wherein said first type is adapted to receive a first set of inputs and wherein said second type is adapted to receive a second set of inputs different from said first set.

19. The array of analog blocks of claim 17 wherein said array comprises a first row of continuous time blocks and multiple rows of switched capacitor blocks, wherein said first row is disposed between a row of switched capacitor blocks and an edge of said array.

20. The array of analog blocks of claim 19 wherein each analog block in a column is coupled to a respective digital bus.

21. The array of analog blocks of claim 17 wherein an analog function is an amplifier function, a digital-to-analog converter function, an analog-to-digital converter function, an analog driver function, a low band pass filter function, or a high band pass filter function.

22. The array of analog blocks of claim 17 wherein an analog block comprises a plurality of analog elements having changeable characteristics, wherein a characteristic of an analog element is specified according to said particular analog function.