High-performance, superscalar-based computer system with out-of-order instruction execution
First Claim
1. A computer system, comprising:
- a memory;
a superscalar microprocessor for processing instructions; and
a bus coupled between the memory and the microprocessor;
wherein the microprocessor includes;
an instruction fetch unit configured to fetch instructions from an instruction store according to a sequential program order;
an instruction buffer coupled to receive and buffer fetched instructions from the instruction fetch unit;
a plurality of functional units configured to execute instructions, thereby generating result data;
a register file including a plurality of entries configured to store data including result data generated by the plurality of functional units, wherein each of the plurality of entries is accessible by reference to a respective location in the register file;
a resource identifying circuit configured to concurrently identify execution resources for more than one of a plurality of buffered instructions, the identified execution resources for each of the buffered instructions including a functional unit capable of executing the instruction and a register file entry corresponding to a source of an operand for the instruction, thereby making a plurality of instructions concurrently available for execution;
an issue control circuit coupled to the resource identifying circuit and configured to concurrently issue more than one of a plurality of available instructions to the functional units for execution, based on availability of the execution resources identified by the resource identifying circuit and without regard to the sequential program order;
a plurality of data routing paths coupled between the plurality of functional units and the register file and configured to concurrently transfer result data from more than one of the plurality of functional units to the register file; and
bypass control logic coupled to the plurality of data routing paths and configured to distribute result data from a first one of the plurality of functional units as operand data for another one or more of the plurality of functional units via an alternate data path that bypasses the register file, wherein distributing result data via the alternate data path occurs concurrently with transferring result data to the register file.
0 Assignments
0 Petitions
Accused Products
Abstract
A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.
-
Citations
23 Claims
-
1. A computer system, comprising:
-
a memory;
a superscalar microprocessor for processing instructions; and
a bus coupled between the memory and the microprocessor;
wherein the microprocessor includes;
an instruction fetch unit configured to fetch instructions from an instruction store according to a sequential program order;
an instruction buffer coupled to receive and buffer fetched instructions from the instruction fetch unit;
a plurality of functional units configured to execute instructions, thereby generating result data;
a register file including a plurality of entries configured to store data including result data generated by the plurality of functional units, wherein each of the plurality of entries is accessible by reference to a respective location in the register file;
a resource identifying circuit configured to concurrently identify execution resources for more than one of a plurality of buffered instructions, the identified execution resources for each of the buffered instructions including a functional unit capable of executing the instruction and a register file entry corresponding to a source of an operand for the instruction, thereby making a plurality of instructions concurrently available for execution;
an issue control circuit coupled to the resource identifying circuit and configured to concurrently issue more than one of a plurality of available instructions to the functional units for execution, based on availability of the execution resources identified by the resource identifying circuit and without regard to the sequential program order;
a plurality of data routing paths coupled between the plurality of functional units and the register file and configured to concurrently transfer result data from more than one of the plurality of functional units to the register file; and
bypass control logic coupled to the plurality of data routing paths and configured to distribute result data from a first one of the plurality of functional units as operand data for another one or more of the plurality of functional units via an alternate data path that bypasses the register file, wherein distributing result data via the alternate data path occurs concurrently with transferring result data to the register file. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. A superscalar microprocessor for processing instructions, the microprocessor comprising:
-
an instruction fetch unit configured to fetch instructions from an instruction store according to a sequential program order;
an instruction buffer coupled to receive and buffer fetched instructions from the instruction fetch unit;
a plurality of functional units configured to execute instructions, thereby generating result data;
a register file including a plurality of entries configured to store data including result data generated by the plurality of functional units, wherein each of the plurality of entries is accessible by reference to a respective location in the register file;
a resource identifying circuit, disposed at a stage subsequent to said instruction buffer, configured to concurrently identify execution resources for a plurality of buffered instructions, thereby making a plurality of instructions concurrently available for issue, wherein the identified execution resources for each of the available instructions include a functional unit capable of executing the instruction and a register file entry corresponding to a source of an operand for the instruction; and
an issue control circuit coupled to the resource identifying circuit and configured to concurrently issue more than one the available instructions to the functional units for execution, based on availability of the identified execution resources for each instruction and without regard to the sequential program order. - View Dependent Claims (10, 11, 12, 13)
-
-
14. A method for processing instructions in a superscalar microprocessor, the method comprising:
-
fetching instructions from an instruction store according to a sequential program order;
buffering a plurality of fetched instructions in an instruction buffer;
concurrently identifying execution resources, by a resource identifying circuit disposed at a stage subsequent to said instruction buffer, for more than one of a plurality of buffered instructions, the identified execution resources for each of the more than one of the plurality of buffered instructions including a functional unit capable of executing the instruction and a register file entry corresponding to a source of an operand for the instruction;
concurrently making available for execution a plurality of instructions for which execution resources are identified;
concurrently issuing more than one of the plurality of available instructions for execution by a plurality of functional units, based on availability of the identified execution resources for each available instruction and without regard to the sequential program order;
executing the issued instructions in the plurality of functional units, thereby generating result data; and
transferring the result data from the functional units to a register file, the register file including a plurality of entries, wherein each of the plurality of entries is accessible by reference to a respective location in the register file. - View Dependent Claims (15, 16, 17, 18)
-
-
19. A computer system, comprising:
-
a memory;
a superscalar microprocessor for processing instructions; and
a bus coupled between the memory and the microprocessor;
wherein the microprocessor includes;
an instruction fetch unit configured to fetch instructions from an instruction store according to a sequential program order;
an instruction buffer coupled to receive fetched instructions from the instruction fetch unit and configured to buffer a plurality of fetched instructions;
a plurality of functional units configured to execute instructions, thereby generating result data;
a register file including a plurality of entries configured to store data including result data generated by the plurality of functional units, wherein each of the plurality of entries is accessible by reference to a respective location in the register file;
a resource identifying circuit, disposed at a stage subsequent to said instruction buffer, configured to concurrently identify execution resources for a plurality of buffered instructions, the identified execution resources for each of the buffered instructions including a functional unit capable of executing the instruction and a register file entry corresponding to a source of an operand for the instruction, thereby making a plurality of instructions concurrently available for execution; and
an issue control circuit coupled to the resource identifying circuit and configured to concurrently issue more than one of the available instructions to the functional units for execution, based on availability of the execution resources identified by the resource identifying circuit and without regard to the sequential program order. - View Dependent Claims (20, 21, 22, 23)
-
Specification