Bus capability voting mechanism
First Claim
1. A computer system comprising:
- a backplane that includes;
multiple sockets;
a bus that couples the multiple sockets together, wherein the bus includes a capability signal line; and
a circuit board inserted in one of the multiple sockets, and configured with a zener device to limit a voltage on the capability signal line to one of three or more predetermined values, wherein the predetermined values are indicative of different bus component capability levels.
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Accused Products
Abstract
A computer system is disclosed having a bus capability determination mechanism. In a preferred embodiment, the computer system includes a backplane having sockets into which system and peripheral boards may be inserted. The sockets are coupled together by a backplane bus that includes a bus capability line. Each board preferably includes a voting circuit that, when enabled, limits the voltage on the capability signal line to no more than a predetermined voltage that is indicative of the capability of the board. The voltage on the capability signal line will thus be determined by the board having the lowest voltage limit. The clock source for the bus can then be set to the clock rate indicated by the voltage on the capability signal line. Zener devices are preferably used to carry out the voting operation, and may be disabled after the voting operation is complete.
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Citations
20 Claims
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1. A computer system comprising:
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a backplane that includes;
multiple sockets;
a bus that couples the multiple sockets together, wherein the bus includes a capability signal line; and
a circuit board inserted in one of the multiple sockets, and configured with a zener device to limit a voltage on the capability signal line to one of three or more predetermined values, wherein the predetermined values are indicative of different bus component capability levels. - View Dependent Claims (2, 3, 4, 7, 8, 9)
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5. A computer system comprising:
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a backplane that includes;
multiple sockets;
a bus that couples the multiple sockets together, wherein the bus includes a capability signal line; and
a circuit board inserted in one of the multiple sockets, and configured to limit a voltage on the capability signal line to one of three or more predetermined values, wherein the predetermined values are indicative of different bus component capability levels, wherein the circuit board includes a voting circuit that limits the voltage on the capability signal line when the voting circuit is enabled, wherein the circuit board further includes a sample circuit that latches a digital value indicative of the voltage on the capability signal line. - View Dependent Claims (6)
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10. A computer system comprising:
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a processor;
a memory coupled to the processor;
a peripheral bus, wherein the peripheral bus includes a capability signal line having a voltage that is limited to a predetermined voltage that is one of three or more predetermined voltages each being indicative of a different capability level;
a bridge device coupled between the processor and the peripheral bus;
a long-term storage device coupled to the bridge device; and
one or more peripheral components coupled to the peripheral bus, wherein each peripheral component is configured with a zener diode to limit the voltage on the capability signal line to a corresponding predetermined voltage that is indicative of a corresponding capability level of the peripheral component. - View Dependent Claims (11, 12)
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13. A computer system comprising:
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a processor;
a memory coupled to the processor;
a peripheral bus, wherein the peripheral bus includes a capability signal line having a voltage that is limited to a predetermined voltage that is one of three or more predetermined voltages each being indicative of a different capability level;
a bridge device coupled between the processor and the peripheral bus;
a long-term storage device coupled to the bridge device; and
one or more peripheral components coupled to the peripheral bus, wherein each peripheral component is configured to limit the voltage on the capability signal line to a corresponding predetermined voltage that is indicative of a corresponding capability level of the peripheral component, wherein each peripheral component includes a voting circuit that limits the voltage on the capability signal line when a peripheral bus reset signal is asserted.
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14. A method of determining a maximum bus clock rate supported by various components, the method comprising:
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coupling the components to a bus having a capability signal line;
supplying electrical current to the capability signal line, wherein each of the components limits a voltage on the capability signal line to no more than a predetermined voltage that is indicative of a maximum bus clock rate supported by the component, each predetermined voltage being one of a set of three or more predetermined voltages that are indicative of different maximum clock rates;
setting a bus clock rate to the maximum clock rate associated with the voltage on the capability signal line; and
asserting a bus reset signal while supplying electrical current to the capability signal line. - View Dependent Claims (15, 18, 19, 20)
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16. A method of determining a maximum bus clock rate supported by various components, the method comprising:
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coupling the components to a bus having a capability signal line;
supplying electrical current to the capability signal line, wherein each of the components limits a voltage on the capability signal line to no more than a predetermined voltage that is indicative of a maximum bus clock rate supported by the component, each predetermined voltage being one of a set of three or more predetermined voltages that are indicative of different maximum clock rates; and
setting a bus clock rate to the maximum clock rate associated with the voltage on the capability signal line, wherein the components include zener devices configured in accordance the maximum bus clock rate supported by the components. - View Dependent Claims (17)
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Specification