Method and system for integrating cores in FPGA-based system-on-chip (SoC)
First Claim
Patent Images
1. A method for customization of a FPGA-based SoC design, the method comprising:
- selecting a system design component used for customizing the FPGA-based SoC design;
configuring said selected system design component with parameters for use with the FPGA-based SoC design;
said selected system component sending said parameters used to configure said selected system design component to peer system design components;
configuring said peer system design components using said sent parameters during customization of the FPGA-based SoC design; and
generating hardware description language code from the selected system design components and peer system design components.
1 Assignment
0 Petitions
Accused Products
Abstract
The invention provides an interface that can facilitate integration of user specific proprietary cores and commercially available cores during customization of an FPGA-based SoC. A selected hardware or software system component (380) used for customizing the FPGA-based SoC can be configured (382) using parameters that can be automatically propagated (384) and used to configure peer system components. During configuration (388) of the peer system components, other parameters used to configure those peer system components can also be propagated (400) and used to configure other system components during customization of the FPGA-based SoC.
107 Citations
13 Claims
-
1. A method for customization of a FPGA-based SoC design, the method comprising:
-
selecting a system design component used for customizing the FPGA-based SoC design;
configuring said selected system design component with parameters for use with the FPGA-based SoC design;
said selected system component sending said parameters used to configure said selected system design component to peer system design components;
configuring said peer system design components using said sent parameters during customization of the FPGA-based SoC design; and
generating hardware description language code from the selected system design components and peer system design components. - View Dependent Claims (2, 3, 4, 5)
-
-
6. A machine readable storage having stored thereon, a computer program having a plurality of code sections, said code sections executable by a machine for causing the machine to perform the steps of:
-
selecting a system design component used for customizing a FPGA-based SoC;
configuring said selected system component with parameters for use with said FPGA-based SoC;
said selected system component sending said parameters used to configure said selected system component to peer system components;
configuring said peer system components using said sent parameters during customization of said FPGA-based SoC; and
generating hardware description language code from the selected system design components and peer system design components. - View Dependent Claims (7)
-
-
8. A method for creating a design of a field programmable gate array-based (FPGA-based) system on chip (SoC), comprising:
-
selecting hardware design components from a library in response to user input to a design tool executing on a processor;
associating at least one parameter value with a first selected hardware design component in response to user input to the design tool;
automatically associating by the design tool, without user specification of the association, the at least one parameter value with a second selected hardware design component; and
generating by the design tool hardware description language code from the first and second hardware design components using the at least one parameter value. - View Dependent Claims (9, 10, 11)
-
-
12. An apparatus for creating a design of a field programmable gate array-based (FPGA-based) system on chip (SoC), comprising:
-
means for selecting hardware design components from a library in response to user input to a design tool executing on a processor;
means for associating at least one parameter value with a first hardware design component in response to user input to the design tool;
means for automatically associating by the design tool, without user specification of the association, the at least one parameter value with a second hardware design component; and
means for generating by the design tool hardware description language code from the first and second hardware design components using the at least one parameter value.
-
-
13. A system for creating a design of a field programmable gate array-based (FPGA-based) system on chip (SoC), comprising:
-
a selector module adapted to select, responsive to user input, components from a library of hardware design components and software design components;
a customizer module coupled to the selector module, the customizer module adapted to relate, responsive to user input, parameter values with the selected components, and for at least one parameter value related by a user to a first one of the selected components automatically relate the at least one parameter value to a second one of the selected components without user specification of the relation to the second one of the components;
an analyzer module coupled to the customizer module and adapted to check for inconsistency of parameter values between the selected components; and
a code generator coupled to the customizer module and adapted to generate hardware description language code from the selected components and related parameter values.
-
Specification