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Integrated circuits with persistent data storage

  • US 6,942,155 B1
  • Filed: 05/07/2002
  • Issued: 09/13/2005
  • Est. Priority Date: 05/31/2001
  • Status: Expired due to Term
First Claim
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1. A timing delay circuit, comprising:

  • at least one inverter coupled to an input voltage line;

    a transistor coupled to the at least one inverter;

    a dielectric charge storage portion coupled to the transistor for storing a dielectric capacitance;

    a junction capacitance portion coupled to the transistor for storing a junction capacitance; and

    a logic gate coupled to the dielectric charge storage portion;

    a code comparator coupled to the logic gate, the code comparator to receive a destruct command; and

    wherein the timing delay circuit forms a portion of an RFID device, and wherein the destruct command, when enabled, destroys the RFID device.

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