Integrated circuits with persistent data storage

• US 6,942,155 B1
• Filed: 05/07/2002
• Issued: 09/13/2005
• Est. Priority Date: 05/31/2001
• Status: Expired due to Term

• Current Assignee: RUIZHANG TECHNOLOGY LIMITED COMPANY
• Original Assignee: Alien Technology Corporation
• Inventors: Stewart, Roger G., Rolin, John
• Primary Examiner(s): Kim, Ahshik
• Application Number:
  US10/140,589
• Time in Patent Office: 1,225 Days
• Field of Search: 235/375, 235/492, 235/380, 235/451, 235/487, 327/143, 327/278, 327/281, 340/10.4, 340/10.41
• US Class Current: 235/487
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G06K 19/07381 with deactivation or otherwise incapacitation of at least a part of the circuit upon detected tampering

Abstract

The circuitry introduced in this invention selectively slows down the functioning of an electronic circuit maintaining a particular state for a prolonged period of time. This circuitry is used not only to achieve the desired effect in maintaining security from electronic thieves trying to circumvent codes but also in other applications such as enabling a circuit to continue to function in the event of a brief loss of power. For example, in an RFID system, if a reader is frequency hopping, a tag loses power for as long as about 400 milliseconds when the reader changes to other frequencies. In a preferred embodiment, the disclosed circuitry is used in conjunction with a destruct sequence.

Claims

1. A timing delay circuit, comprising:

at least one inverter coupled to an input voltage line;

a transistor coupled to the at least one inverter;

a dielectric charge storage portion coupled to the transistor for storing a dielectric capacitance;

a junction capacitance portion coupled to the transistor for storing a junction capacitance; and

a logic gate coupled to the dielectric charge storage portion;

a code comparator coupled to the logic gate, the code comparator to receive a destruct command; and

wherein the timing delay circuit forms a portion of an RFID device, and wherein the destruct command, when enabled, destroys the RFID device.

2. The circuit as recited in claim 1, wherein the dielectric capacitance of the dielectric charge storage portion is greater than a junction capacitance of the junction capacitance portion.

3. The circuit as recited in claim 1, wherein a time constant of the dielectric charge storage portion is greater than 100 seconds, wherein a time constant of the junction capacitance portion is less than 1 second.

4. The circuit as recited in claim 1, further comprising three or more inverters on the input voltage line.

5. The circuit as recited in claim 1, wherein the dielectric charge storage portion is a dielectric capacitor.

6. The circuit as recited in claim 1, wherein the transistor is a PMOS transistor.

7. The circuit as recited in claim 1, wherein the transistor is an NMOS transistor.

8. The circuit as recited in claim 1, wherein the circuit is an extended duration one-shot circuit.

9. The circuit as recited in claim 1, further comprising a disabling portion coupled to the logic gate, the disabling portion for disabling the RFID device.