Method of fabricating heterojunction photodiodes integrated with CMOS

• US 6,943,051 B2
• Filed: 10/12/2001
• Issued: 09/13/2005
• Est. Priority Date: 10/19/2000
• Status: Expired due to Term

• Current Assignee: Quantum Semiconductor LLC
• Original Assignee: Quantum Semiconductor LLC
• Inventors: Augusto, Carlos J. R. P., Forester, Lynn
• Primary Examiner(s): Pham, Long
• Assistant Examiner(s): Trinh, (Vicki) Hoa B.
• Application Number:
  US10/399,495
• Publication Number:
  US 20040097021A1
• Time in Patent Office: 1,432 Days
• Field of Search: 438/58, 438/48, 438/57, 438/30, 438/154
• US Class Current: 438/58
• CPC Class Codes: B82Y 20/00 Nanooptics, e.g. quantum optics or photonic crystals
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H01L 27/14692 Thin film technologies, e.g. amorphous, poly, micro- or nanocrystalline silicon

Abstract

A method in which thin-film p-i-n heterojunction photodiodes are formed by selective epitaxial growth/deposition on pre-designated active-area regions of standard CMOS devices. The thin-film p-i-n photodiodes are formed on active areas (for example n⁺-doped), and these are contacted at the bottom (substrate) side by the “well contact” corresponding to that particular active area. There is no actual potential well since that particular active area has only one type of doping. The top of each photodiode has a separate contact formed thereon. The selective epitaxial growth of the p-i-n photodiodes is modular, in the sense that there is no need to change any of the steps developed for the “pure” CMOS process flow. Since the active region is epitaxially deposited, there is the possibility of forming sharp doping profiles and band-gap engineering during the epitaxial process, thereby optimizing several device parameters for higher performance. This new type of light sensor architecture, monolithically integrated with CMOS, decouples the photo-absorption active region from the MOSFETs, hence the bias applied to the photodiode can be independent from the bias between the source, drain, gate and substrate (well) of the MOSFETs.

Claims

1. A method of fabricating a photodiode module monolithically integrated with a CMOS structure in a semiconductor substrate, comprising the steps of:

(a) In said semiconductor substrate, forming at least one photo-diode active area surrounded by field oxide (FOX) regions, using any isolation technologies of CMOS processes, said photo-diode active area containing at least one embedded well semiconductor region implanted therein, said embedded well semiconductor region having a defined polarity, said embedded semiconductor well being surrounded laterally and underneath by semiconductor regions implanted with doping impurities of the opposite polarity, said embedded semiconductor well extending itself under a selected portion of the surrounding field oxide regions and overlapping at least a fraction of a selected adjacent active area, said overlapped fraction of adjacent active area including a surface region with high doping concentration of the same polarity of the embedded semiconductor well;

(b) epitaxially growing photosensitive layers on said at least one photo-diode active area, said photosensitive layers comprising at least a doped semiconductor material having the opposite polarity as that of the embedded well semiconductor region underneath;

(c) forming an ohmic contact region on at least one selected area of each of said epitaxially grown photosensitive layers;

(d) forming a columnar metal interconnect layer on top of each selected area of said epitaxially grown photosensitive layer; and

(e) forming a planarized dielectric layer on the non-selected areas of said epitaxially grown photosensitive layers up to the top level of said metal interconnect layer.

2. The method as claimed in claim 1, wherein the epitaxial grow of photosensitive layers takes place in the CMOS process flow after formation of lightly doped drain (LDD) and source regions for CMOS devices, but before the highly doped drain (HDD) and source regions of CMOS devices are formed.

3. The method as claimed in claim 1, wherein the epitaxial grow of photosensitive layers takes place in the CMOS process flow after formation of highly doped drain (HDD) and source regions for CMOS devices, but before silicide is formed.

4. The method as claimed in claim 1, wherein said overlapped fraction of adjacent active area by the embedded well, is part of the source/drain region of a MOSFET.

5. The method as claimed in claim 1, wherein said overlapped fraction of adjacent active area, by the embedded well, includes surface region with same polarity of the semiconductor well, having a high doping concentration, suitable for the formation of an ohmic contact such as that provided by a silicide.

6. The method as claimed in claim 1, wherein said contact layer is an opaque conducting material.

7. The method as claimed in claim 1, wherein said contact layer is a light-transparent conducting material.

8. An image sensor fabricated according to the method of claim 1, wherein said at least one embedded well semiconductor region is isolated from at least one second embedded well semiconductor region, said at least one second embedded well semiconductor region forming part of a semiconductor charge storage device.

9. A heterojunction photodiode module monolithically integrated with a CMOS, fabricated according to the method of claim 1, wherein said photodiode comprises a stack of epitaxially deposited layers with pseudomorphic random alloys and/or superlattices and/or quantum well films of at least one material selected from the group comprising SiGe, SiGeC, GeC, SiSn, SiGeSn, SiCSn, SiGeCSn.

10. A heterojunction photodiode module monolithically integrated with a CMOS, fabricated according to the method of claim 1, wherein said photodiode comprises a stack of epitaxially deposited layers with pseudomorphic random alloys and/or superlattices and/or quantum well films of at least one material selected from the group comprising PbTe, PbSnSe, ZnS, GaN, AlN, Al₂O₃, LaAl₂O₃, Pr₂O₃, CeO₂, CaF₂, Sr₂TiO₄, SrTiO ₃.

11. A CMOS image sensor incorporating at least one photodiode module fabricated according to the method of claim 1, with photodiode epitaxial layers according to claim 9.

12. A CMOS image sensor incorporating at least one photodiode module fabricated according to the method of claim 1 with photodiode epitaxial layers according to claim 10.