Three-dimensional integrated semiconductor devices

• US 6,943,067 B2
• Filed: 09/30/2002
• Issued: 09/13/2005
• Est. Priority Date: 01/08/2002
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Greenlaw, David
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): HOANG, QUOC DINH
• Application Number:
  US10/260,840
• Publication Number:
  US 20030129829A1
• Time in Patent Office: 1,079 Days
• Field of Search: 438/152, 438/153, 438/618
• US Class Current: 438/152
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention describes a process for three-dimensional integration of semiconductor devices and a resulting device. The process combines low temperature wafer bonding methods with backside/substrate contact processing methods, preferably with silicon on insulator devices. The present invention utilizes, in an inventive fashion, low temperature bonding processes used for bonded silicon on insulator (SOI) wafer technology. This low temperature bonding technology is adopted for stacking several silicon layers on top of each other and building active transistors and other circuit elements in each one. The back-side/substrate contact processing methods allow the interconnection of the bonded SOI layers.

Claims

1. A method of forming a three-dimensional integrated semiconductor device, comprising:

providing a first device member, said first device member comprising a first circuit element formed at least partially in a first semiconductor film, wherein said semiconductor film is formed as a semiconductor island surrounded by insulating material, a first contact portion, and a first planar insulating layer of dielectric material having a first free surface;

providing a second device member, said second device member comprising a second circuit element formed at least partially in a second semiconductor film and a second planar insulating layer of dielectric material formed on the second semiconductor film having a second free surface;

stacking said first and second device members on top of each other such that said first free surface of said first planar insulating layer faces said second free surface of said second planar insulating layer;

bonding said first planar insulating layer and said second planar insulating layer together; and

forming a second contact portion extending through said second device member, said second semiconductor layer, said second planar insulating layer and said first planar insulating layer to said first contact portion.

2. The method of claim 1, wherein at least one of said first and second semiconductor films is formed on an isolating substrate by depositing a silicon layer on said substrate.

3. The method of claim 2, wherein at least one of said first and second device members is formed by a process, comprising:

bonding a first semiconductor wafer to a second semiconductor wafer, wherein at least one semiconductor wafer surface is oxidized and the oxidized surface lies between the two semiconductor wafers;

etching one of grooves and trenches in one side of the bonded wafers down to said oxidized surface to define silicon islands;

filling the one of grooves and trenches with insulating dielectric material; and

forming circuit elements on said silicon islands.

4. The method of claim 3, wherein said first and said second semiconductor wafers are bonded together at a temperature range from approximately 700-1200°

C.

5. The method of claim 3, wherein said first and said second semiconductor wafers are bonded by using the same bonding process as for the bonding of said first and second planar insulating layers of said first and second device members.

6. The method of claim 1, wherein silicon dioxide is used as said dielectric material.

7. The method of claim 1, wherein forming said first contact portion comprises:

etching a via into said first device member through at least two different materials; and

filling said via with conductive material.

8. The method of claim 7, wherein said first contact portion comprises a substrate contact providing a conductive path to a substrate on which said first device member is formed.

9. The method of claim 7, wherein an aspect ratio of said via is larger than 10.

10. The method of claim 7, wherein an aspect ratio of said via is larger than 15.

11. The method of claim 7, wherein an anisotropic dry etch process is used to etch said via into said first device member.

12. The method of claim 1, wherein the bonding of said first and said second device comprises:

polishing the first and second free surfaces of the first and the second planar insulating layers;

activating the first and second free surfaces; and

bringing said polished first and second free surfaces into close contact.

13. The method of claim 1, wherein said first and said second devices are bonded at a temperature range approximately between room temperature and 500°

C.

14. The method of claim 1, wherein said first and said second devices are bonded at a temperature range approximately between room temperature and 300°

C.

15. The method of claim 1, wherein forming of said second contact portion comprises:

etching a via extending through said second device member, said second semiconductor layer, said second planar insulating layer and said first planar insulating layer to a first contact portion; and

filling said via with a conductive material.

16. The method of claim 15, wherein an aspect ratio of said via is larger than 10.

17. The method of claim 15, wherein an aspect ratio of said via is larger than 15.

18. The method of claim 15, wherein an anisotropic dry etch process is used to etch said via extending through said second device.

19. The method of claim 1, wherein providing said second semiconductor device member further comprises:

depositing a bonding layer on the surface;

attaching a temporary substrate used as supporting layer; and

removing a substrate underlying said second planar insulating layer of dielectric material.

20. The method of claim 19, wherein the supporting layer is chosen to be compatible to underlying structures regarding thermal expansion.

21. The method of claim 19, wherein said temporary substrate is removed after bonding said second planar insulating layer to said first planar insulating layer.

22. A method of forming a three-dimensional integrated semiconductor device, comprising:

providing a first semiconductor circuit element, said first semiconductor circuit element comprising a first contact portion and a first planar insulating layer of dielectric material covering said first semiconductor circuit element and said first contact portions and having a first free surface;

providing a second semiconductor circuit element formed on a second planar insulating layer of dielectric material having a second free surface;

stacking said first and said second semiconductor circuit elements on top of each other such that said first free surface of said first planar insulating layer faces said second free surface of said second planar insulating layer;

bonding said first planar insulating layer and said second planar insulating layer together; and

forming a second contact portion extending through said second semiconductor circuit element, said second planar insulating layer and said first planar insulating layer to a first contact portion by etching a via having an aspect ratio greater than 10 and filling it with conductive material.

23. The method of claim 22, wherein an aspect ratio of said via is larger than 15.

24. The method of claim 22, wherein at least one of said first and second semiconductor circuit elements is formed on and in a silicon layer deposited on an insulating substrate.

25. The method of claim 24, wherein at least one of said first and said second semiconductor circuit elements is formed by a process comprising:

bonding a first semiconductor wafer to a second semiconductor wafer, wherein at least one semiconductor wafer surface is oxidized and the oxidized surface lies between the two semiconductor wafers;

etching one of grooves and trenches in one side of the bonded wafers down to said oxidized surface to define silicon islands;

filling the one of grooves and trenches with insulating dielectric material; and

forming circuit elements on said silicon islands.

26. The method of claim 25, wherein said first and said second semiconductor wafers are bonded together at a temperature ranging from approximately 700-1200°

C.

27. The method of claim 25, wherein said first and said second semiconductor wafers are bonded together by using the same bonding process as for the bonding of said first and second planar insulating layers of said first and second semiconductor circuit elements.

28. The method of claim 22, wherein silicon dioxide is used as said dielectric material.

29. The method of claim 22, wherein forming said first contact portion comprises:

etching a via into said first device member through at least two different materials; and

filling said via with conductive material.

30. The method of claim 29, wherein said first contact portion comprises a substrate contact providing a conductive path to a substrate on which said first semiconductor circuit element is formed.

31. The method of claim 29, wherein an aspect ratio of said via is larger than 10.

32. The method of claim 29, wherein an aspect ratio of said via is larger than 15.

33. The method of claim 29, wherein an anisotropic dry etch process is used to etch said via into said first device.

34. The method of claim 22, wherein the bonding of said first and said second devices comprises:

polishing the first and second free surfaces of the first and the second planar insulating layers;

activating the first and second free surfaces; and

bringing said polished first and second free surfaces into close contact.

35. The method of claim 34, wherein said first and said second devices are bonded together at a temperature range approximately between room temperature and 500°

C.

36. The method of claim 34, wherein said first and said second devices are bonded together at a temperature range approximately between room temperature and 300°

C.

37. The method of claim 22, wherein providing said second semiconductor circuit element further comprises:

depositing a bonding layer on the surface;

attaching a temporary substrate used as a supporting layer; and

removing a substrate underlying said second planar insulating layer of dielectric material.

38. The method of claim 37, wherein the supporting layer is chosen to be compatible to underlying structures regarding thermal expansion.

39. The method of claim 38, wherein said temporary substrate is removed after bonding said second planar insulating layer to said first planar insulating layer.

40. A method of forming a three-dimensional integrated semiconductor device, comprising:

providing a first semiconductor device element, said first semiconductor device element comprising at least two circuit elements stacked on top of each other and fused together, a first contact portion and a first planar insulating layer of dielectric material having a first free surface;

providing a second semiconductor device element formed on a second planar insulating layer of dielectric material having a second free surface;

stacking said first and said second semiconductor device elements on top of each other such that said first free surface of said first planar insulating layer faces said second free surface of said second planar insulating layer;

bonding said first planar insulating layer and said second planar insulating layer together; and

forming a second contact portion extending through said second semiconductor device element, said second planar insulating layer and said first planar insulating layer to said first contact portion by etching at least one via having an aspect ratio greater than 10 and filling it with conductive material.

41. The method of claim 40, wherein at least one of said circuit elements is formed in and on a silicon layer deposited on an insulating substrate.

42. The method of claim 40, wherein at least one of said first and second semiconductor device elements is formed in and on a silicon layer deposited on an insulating substrate.

43. The method of claim 40, wherein silicon dioxide is used as said dielectric material.

44. The method of claim 40, wherein forming one of said first and said second contact portions comprises:

etching a via through at least two different materials; and

filling said via with conductive material.

45. The method of claim 44, wherein one of said first and said second contact portions comprises a substrate contact providing a conductive path to a substrate on which one of said first and said second semiconductor device elements is formed.

46. The method of claim 44, wherein an aspect ratio of said via is larger than 15.

47. The method of claim 40, wherein the bonding of said first and said second devices comprises:

polishing the first and second free surfaces of the first and the second planar insulating layer;

activating the first and second free surfaces; and

bringing said polished first and second free surfaces into close contact.

48. The method of claim 47, wherein said first and said second devices are bonded together at a temperature range approximately between room temperature and 500°

C.

49. The method of claim 47, wherein said first and said second devices are bonded together at a temperature range approximately between room temperature and 300°

C.

50. A method of forming a three-dimensional integrated semiconductor device, comprising:

providing a first semiconductor film with a first planar insulating layer of dielectric material having a first free surface;

providing a second semiconductor film with a second planar insulating layer of dielectric material having a second free surface;

stacking said first and said second semiconductor films on top of each other such that said first free surface of said first planar insulating layer faces said second free surface of said second planar insulating layer and such that the first and the second semiconductor films are separated by the first and the second planar insulating layers;

bonding said first planar insulating layer and said second planar insulating layer together;

forming a circuit element at least partially in each of said first and second semiconductor films; and

forming a contact portion by etching a via having an aspect ratio greater than 10 and filling it with conductive material.

51. The method of claim 50, wherein at least one of said circuit elements is formed in and on a silicon layer deposited on an insulating substrate.

52. The method of claim 50, wherein silicon dioxide is used as said dielectric material.

53. The method of claim 50, wherein forming said contact portion comprises:

etching a via through at least two different materials; and

filling said via with conductive material.

54. The method of claim 53, wherein said contact portion comprises a substrate contact providing a conductive path to a substrate on which said circuit element is formed.

55. The method of claim 53, wherein said contact portion provides an interconnection between first and second circuit elements of said first and second semiconductor films.

56. The method of claim 53, wherein an aspect ratio of said via is larger than 15.

57. The method of claim 50, wherein the bonding of said first and said second planar insulating layers comprises:

polishing the first and second free surfaces of the first and the second planar insulating layers;

activating the first and second free surfaces; and

bringing said first and second free polished surfaces into close contact.

58. The method of claim 57, wherein said first and said second devices are bonded together at a temperature range approximately between room temperature and 500°

C.

59. The method of claim 57, wherein said first and said second devices are bonded together at a temperature range approximately between room temperature and 300°

C.