Non-volatile memory cells having floating gate and method of forming the same

• US 6,943,403 B2
• Filed: 09/23/2003
• Issued: 09/13/2005
• Est. Priority Date: 12/20/2002
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Sung-Chul
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): HOANG, QUOC DINH
• Application Number:
  US10/669,795
• Publication Number:
  US 20040119110A1
• Time in Patent Office: 721 Days
• Field of Search: 257/314, 257/315, 257/316, 257/317
• US Class Current: 257/317
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A non-volatile memory cell having a floating gate and a method of forming the same. The non-volatile memory cell includes a device isolation layer that is formed in a semiconductor substrate and defines an active region. A floating gate is disposed over the active region and is comprised of a plurality of first conductive patterns and a plurality of second conductive patterns that are alternately stacked. A first insulation layer is disposed between the floating gate and the active region. One of the first conductive pattern and the second conductive pattern protrudes to form concave and convex sidewalls of the floating gate. Therefore, a surface area of the floating gate increases, thereby raising coupling ratio between the floating gate and the control gate electrode. As a result, an operating voltage of the non-volatile memory cell can be reduced.

Claims

1. A non-volatile memory cell comprising:

a device isolation layer disposed in a substrate to define an active region;

a floating gate disposed over the active region and comprised of a plurality of first conductive patterns and a plurality of second conductive patterns which are alternately stacked; and

a first insulation layer interposed between the floating gate and the active region, wherein one of the first and second conductive patterns protrudes to form concave and convex shaped sidewalls of the floating gate.

2. The non-volatile memory cell of claim 1, wherein one of the first and second conductive patterns is formed of doped polysilicon layers and the other of the first and second conductive patterns is formed of doped silicon germanium layers.

3. The nonvolatile memory cell of claim 2, wherein the doped polysilicon layers protrude to form convex portions of the sidewalls of the floating gate and the doped silicon germanium layers forms concave portion of the sidewalls of the floating gate.

4. The non-volatile memory cell of claim 1, further comprising:

a control gate electrode disposed over the floating gate and crossing over the active region; and

a gate interlayer dielectric pattern disposed between the control gate electrode and the floating gate,

wherein the gate interlayer dielectric pattern and the control gate electrode are disposed over a top surface and the concave and convex sidewalls of the floating gate.

5. The non-volatile memory cell of claim 4, further comprising impurity diffusion layers formed in the active region at sides of the control gate electrode.

6. The non-volatile memory cell of claim 4, further comprising:

a selection gate pattern crossing over the active region at one side of the control gate electrode;

a floating impurity diffusion layer disposed in the active region between the selection gate pattern and the control gate electrode; and

an impurity diffusion layer respectively formed in the active region that is beside the selection gate pattern and opposite to one side of the floating impurity diffusion layer, and in the active region that is beside the floating gate and opposite another side of the floating impurity diffusion layer,

wherein a portion of the floating impurity diffusion layer overlaps a portion of the floating gate.

7. The non-volatile memory cell of claim 6, further comprising:

a tunnel window region including a predetermined bottom region of the floating gate and the active region thereunder; and

a second insulation layer disposed between the floating gate and the active region in the tunnel window region,

wherein the tunnel window region is disposed in the overlapping region of the floating gate and the floating impurity diffusion layer, and the second insulation layer is thinner than the first insulation layer.

8. The non-volatile memory cell of claim 6, wherein the selection gate pattern comprises a first selection gate electrode, a selection gate dielectric pattern and a second selection gate electrode,

wherein the first selection gate electrode is formed of the same material layer as the floating gate, the selection gate dielectric pattern is formed of the same material layer as the gate interlayer dielectric pattern, and the second selection gate electrode is formed of the same material layer as the control gate electrode.

9. A non-volatile memory cell comprising:

substrate;

an active region formed in the substrate; and

a floating gate having sidewalls formed over the active region, the sidewalls having protruding portions, wherein the floating gate comprises a plurality of first conductive patterns and a plurality of second conductive patterns, and wherein one of the plurality of first conductive patterns and the plurality of second conductive.

10. The non-volatile memory of claim 9, wherein one of the plurality of first conductive patterns and the plurality of second conductive patterns is formed of doped polysilicon layers and the other of the plurality of first conductive patterns and the plurality of second conductive patterns is formed of doped silicon germanium layers.

11. The non-volatile memory of claim 10, wherein the doped polysilicon layers form the protruding portions of the sidewalls.