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Low leakage heterojunction vertical transistors and high performance devices thereof

  • US 6,943,407 B2
  • Filed: 06/17/2003
  • Issued: 09/13/2005
  • Est. Priority Date: 06/17/2003
  • Status: Expired due to Fees
First Claim
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1. A field effect transistor comprising:

  • a substrate, a first single crystalline silicon region having a p-type concentration level greater than 1×

    1019 atoms/cm3 on said substrate, a second carbon-doped epitaxial region over said first crystalline silicon region having a p-type concentration level greater than 1×

    1019 atoms/cm3, a third silicon epitaxial region over said second carbon-doped region doped n-type, a fourth compressively strained Sil-w-q epitaxial region over said third silicon epitaxial region, said Sil-w-q region having a p-type concentration level greater than 1×

    1019 atoms/cm3, a fifth silicon containing region over said fourth Sil-w-qGewCq region having a p-type concentration level greater than 1×

    1019 atoms/cm3, a vertical structure comprising at least one sidewall extending from said first silicon region, second region of carbon-doped layer, third region of silicon, fourth region of Sil-w-qGewCq epitaxial region to said fifth region of silicon, a sixth compressively strained Sil-sGes region over a region of said at least one sidewall of said vertical structure extending from said second region of carbon-doped layer, over said third region of silicon to said fourth region of Sil-sGewCq epitaxial region, a gate dielectric region over said sixth compressively strained Sil-w-qGes region, and a gate conducting region over said dielectric region.

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