Low leakage heterojunction vertical transistors and high performance devices thereof
First Claim
1. A field effect transistor comprising:
- a substrate, a first single crystalline silicon region having a p-type concentration level greater than 1×
1019 atoms/cm3 on said substrate, a second carbon-doped epitaxial region over said first crystalline silicon region having a p-type concentration level greater than 1×
1019 atoms/cm3, a third silicon epitaxial region over said second carbon-doped region doped n-type, a fourth compressively strained Sil-w-q epitaxial region over said third silicon epitaxial region, said Sil-w-q region having a p-type concentration level greater than 1×
1019 atoms/cm3, a fifth silicon containing region over said fourth Sil-w-qGewCq region having a p-type concentration level greater than 1×
1019 atoms/cm3, a vertical structure comprising at least one sidewall extending from said first silicon region, second region of carbon-doped layer, third region of silicon, fourth region of Sil-w-qGewCq epitaxial region to said fifth region of silicon, a sixth compressively strained Sil-sGes region over a region of said at least one sidewall of said vertical structure extending from said second region of carbon-doped layer, over said third region of silicon to said fourth region of Sil-sGewCq epitaxial region, a gate dielectric region over said sixth compressively strained Sil-w-qGes region, and a gate conducting region over said dielectric region.
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Abstract
A method for forming and the structure of a vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry are described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (i.e., B and P) into the body. The invention reduces the problem of short channel effects such as drain induced barrier lowering and the leakage current from the source to drain regions via the hetero-junction and while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials. The problem of scalability of the gate length below 100 nm is overcome by the heterojunction between the source and body regions.
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Citations
28 Claims
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1. A field effect transistor comprising:
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a substrate, a first single crystalline silicon region having a p-type concentration level greater than 1×
1019 atoms/cm3 on said substrate,a second carbon-doped epitaxial region over said first crystalline silicon region having a p-type concentration level greater than 1×
1019 atoms/cm3,a third silicon epitaxial region over said second carbon-doped region doped n-type, a fourth compressively strained Sil-w-q epitaxial region over said third silicon epitaxial region, said Sil-w-q region having a p-type concentration level greater than 1×
1019 atoms/cm3,a fifth silicon containing region over said fourth Sil-w-qGewCq region having a p-type concentration level greater than 1×
1019 atoms/cm3,a vertical structure comprising at least one sidewall extending from said first silicon region, second region of carbon-doped layer, third region of silicon, fourth region of Sil-w-qGewCq epitaxial region to said fifth region of silicon, a sixth compressively strained Sil-sGes region over a region of said at least one sidewall of said vertical structure extending from said second region of carbon-doped layer, over said third region of silicon to said fourth region of Sil-sGewCq epitaxial region, a gate dielectric region over said sixth compressively strained Sil-w-qGes region, and a gate conducting region over said dielectric region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. An inverter comprising:
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a first silicon epitaxial region on a first single crystalline substrate having a n-type concentration level greater than 1×
1019 atoms/cm3,a second Sil-i-jGeiCj epitaxial region over said first n-type silicon region, a third silicon epitaxial region over said second Sil-i-jGeiCj epitaxial region doped p-type, a fourth strained Sil-yCy epitaxial region over said third p-type silicon region having a n-type concentration level greater than 1×
1019 atoms/cm3,a fifth region selected from a group consisting of single crystalline silicon, poly silicon and poly SiGe over said fourth n-type strained Sil-yCy region having a n-type concentration level greater than 1×
1019 atoms/cm3,a first vertical structure comprising at least one sidewall extending from said first silicon region, over said second region of strained Sil-xCx region, over said third region of p-type silicon, over said fourth region of strained Sil-yCy to said fifth region, a sixth silicon region over a region of said at least one sidewall of said vertical structure, a first gate dielectric region over said sixth silicon region, and a first gate conducting region over said gate dielectric region, a seventh p-type silicon epitaxial region on said first single crystalline substrate having a concentration level greater than 1×
1019 atoms/cm3,an eighth carbon-doped epitaxial region over said seventh p-type silicon epitaxial region having a p-type to a concentration level greater than 1×
1019 atoms/cm3,a ninth silicon epitaxial region over said eighth carbon-doped epitaxial region doped n-type, a tenth compressively strained Sil-w-qGewCq epitaxial region over said ninth silicon epitaxial region having a p-type concentration level greater than 1×
1019 atom/cm3,an eleventh region selected from a group consisting of single crystalline silicon, poly silicon and poly SiGe over said tenth Sil-w-qGewCq region having a p-type concentration level greater than 1×
1019 atoms/cm3,a second vertical structure comprising at least one sidewall extending from said seventh p-type silicon region, eighth carbon-doped epitaxial region, ninth silicon epitaxial region, tenth compressively strained Sil-sGewCq epitaxial region, to said eleventh silicon epitaxial region, a twelfth strained Sil-sGes region over a region of said at least one sidewall of said vertical structure, a second gate dielectric region over said twelfth strained Sil-sGes region, and a second gate conducting region over said gate dielectric region. - View Dependent Claims (18, 19, 20, 21, 22)
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23. An inverter comprising:
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a first relaxed Sil-iGei epitaxial region on a first single crystalline substrate said first Sil-iGei epitaxial layer doped n-type to a concentration level greater than 1×
1019 atoms/cm3,a second tensile strained silicon epitaxial region over said first p-type Sil-iGei region, said second silicon epitaxial region doped n-type to a concentration level greater than 1×
1019 atoms/cm3,a third relaxed Sil-iGei epitaxial region over said second silicon region, said third silicon epitaxial region doped p-type, a fourth tensile strained silicon epitaxial region over said third p-type Sil-iGei region, said fourth strained silicon region doped n-type to a concentration level greater than 1×
1019 atoms/cm3,a fifth region selected from a group consisting of relaxed Sil-iGei, poly silicon and poly SiGe over said fourth n-type strained silicon region, said fifth Sil-iGei region doped n-type to a concentration level greater than 1×
1019 atoms/cm3,a first vertical structure comprising at least one sidewall extending from said first relaxed SiGe region, over said second strained silicon epitaxial region, over said third p-type relaxed Sil-iGei epitaxial region, over said fourth strained silicon epitaxial region to said fifth region, a sixth strained silicon region over a region of said at least one sidewall of said first vertical structure, a first gate dielectric region over said sixth silicon region, and a first gate conducting region over said gate dielectric region, a seventh p-type silicon epitaxial region on a first single crystalline substrate having a concentration level greater than 1×
1019 atoms/cm3,an eighth carbon-doped epitaxial region over said seventh p-type silicon epitaxial region having a p-type to a concentration level greater than 1×
1019 atoms/cm3,a ninth silicon epitaxial region over said eighth carbon-doped epitaxial region doped n-type, a tenth compressively strained Sil-w-qGewCq epitaxial region over said ninth silicon epitaxial region having a p-type concentration level greater than 1×
1019 atoms/cm3,an eleventh region selected from a group consisting of single crystalline silicon, poly Si and poly SiGe over said tenth Sil-w-qGewCq region having a p-type concentration level greater than 1×
1019 atoms/cm3,a second vertical structure comprising at least one sidewall extending from said seventh p-type silicon epitaxial region, eighth carbon-doped epitaxial region, ninth silicon epitaxial region, tenth compressively strained Sil-w-qGewCq epitaxial region, to said eleventh silicon epitaxial region, a twelfth strained Sil-sGes region over a region of said at least one sidewall of said second vertical structure, a second gate dielectric region over said twelfth strained Sil-sGes, region, and a second gate conducting region over said gate dielectric region. - View Dependent Claims (24, 25, 26, 27, 28)
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Specification