Low leakage heterojunction vertical transistors and high performance devices thereof

• US 6,943,407 B2
• Filed: 06/17/2003
• Issued: 09/13/2005
• Est. Priority Date: 06/17/2003
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Chu, Jack Oon, Ouyang, Qiqing Christine
• Primary Examiner(s): Baumeister, B. William
• Assistant Examiner(s): Farahani, Dana
• Application Number:
  US10/463,039
• Publication Number:
  US 20040256639A1
• Time in Patent Office: 819 Days
• Field of Search: 257/328, 257/329, 257/330, 257/331, 257/332, 257/333, 257/334, 257/288, 257/350, 257/351, 257/369, 257/372, 438/213, 438/153
• US Class Current: 257/329
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/778 with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence
• CPC Class Codes: H01L 29/7781 with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
• CPC Class Codes: H01L 29/7782 with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
• CPC Class Codes: H01L 29/7789 the two-dimensional charge carrier gas being at least partially not parallel to a main surface of the semiconductor body
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

A method for forming and the structure of a vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry are described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (i.e., B and P) into the body. The invention reduces the problem of short channel effects such as drain induced barrier lowering and the leakage current from the source to drain regions via the hetero-junction and while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials. The problem of scalability of the gate length below 100 nm is overcome by the heterojunction between the source and body regions.

Claims

1. A field effect transistor comprising:

a substrate,

a first single crystalline silicon region having a p-type concentration level greater than 1×

10¹⁹ atoms/cm³ on said substrate,

a second carbon-doped epitaxial region over said first crystalline silicon region having a p-type concentration level greater than 1×

10¹⁹ atoms/cm³,

a third silicon epitaxial region over said second carbon-doped region doped n-type,

a fourth compressively strained Si_l-w-q epitaxial region over said third silicon epitaxial region, said Si_l-w-q region having a p-type concentration level greater than 1×

10¹⁹ atoms/cm³,

a fifth silicon containing region over said fourth Si_l-w-qGe_wC_q region having a p-type concentration level greater than 1×

10¹⁹ atoms/cm³,

a vertical structure comprising at least one sidewall extending from said first silicon region, second region of carbon-doped layer, third region of silicon, fourth region of Si_l-w-qGe_wC_q epitaxial region to said fifth region of silicon,

a sixth compressively strained Si_l-sGe_s region over a region of said at least one sidewall of said vertical structure extending from said second region of carbon-doped layer, over said third region of silicon to said fourth region of Si_l-sGe_wC_q epitaxial region,

a gate dielectric region over said sixth compressively strained Si_l-w-qGe_s region, and a gate conducting region over said dielectric region.

2. The field effect transistor according to claim 1 further including:

a blanket dielectric layer over and above said vertical structure,

a first conducting via through said blanket dielectric layer in contact to said first p-type silicon region,

a second conducting via through said blanket dielectric layer in contact to said fifth p-type silicon containing region at the top of said vertical structure, and

a third conducting via through said blanket dielectric layer in contact to said gate conducting region.

3. The field effect transistor according to claim 1 wherein said fifth silicon containing region is relaxed with respect to the upper surface of said fourth Si_l-w-qGe_wC_q region.

4. The field effect transistor according to claim 1 wherein said fifth silicon containing region is selected from the group consisting of single crystal silicon, poly silicon and poly SiGe.

5. The field effect transistor according to claim 1 wherein said sidewall of said vertical structure is in the crystalline plane (110), and perpendicular to a major surface of said substrate.

6. The field effect transistor according to claim 1 wherein said sixth strained Si_l-sG_s region on said sidewall of said vertical structure is compressively strained with respect to said first silicon region.

7. The field effect transistor according to claim 1 wherein said gate dielectric region is selected from the group consisting of an oxide, nitride, oxynitride of silicon, and oxides and silicates of Hf Al, Zr, La, Y, Ta, singly or in combination thereof.

8. The field effect transistor according to claim 1 wherein said gate conducting region is selected from the group consisting of metal, metal silicide, doped poly silicon and doped poly SiGe.

9. The field effect transistor according to claim 1 wherein said second carbon-doped region is doped p-type in the range from 1×

10¹⁹ to 1×

10²¹ atoms/cm³.

10. The field effect transistor according to claim 1 wherein said fifth silicon containing region is doped p-type in the range from ×

10¹⁹ to 1×

10²¹ atoms/cm³.

11. The field effect transistor according to claim 1 wherein said sixth strained Si_l-sGe_s region is doped p-type in the region adjacent to said first p-type region, second region, fourth region and fifth region while doped n-type in the region adjacent to said third n-type silicon.

12. The field effect transistor according to claim 1 further including a seventh silicon region over said sixth compressively strained Si_l-sGe_s region and below said gate dielectric region.

13. The field effect transistor according to claim 12 wherein said sixth strained Si_l-sGe_s, region and said seventh silicon region are doped p-type in the region adjacent to said first p-type region, second region, fourth region and fifth region while doped n-type in the region adjacent to said third n-type silicon.

14. The field effect transistor according to claim 1 further including an eighth compressively strained Si_l-x-yGe_xC_y epitaxial region over said first silicon region, said eighth compressively strained Si_l-x-yGe_xC_y epitaxial region having a p-type concentration level greater than 1×

10¹⁹ atom/cm³.

15. The field effect transistor according to claim 14 wherein said third silicon region is relaxed with respect to the upper surface of said eighth Si_l-x-yGe_xC_y, region.

16. The field effect transistor according to claim 14 wherein said sixth strained Si_l-sG_s region is doped p-type in the region adjacent to said first p-type region, eighth epitaxial region, fourth region and fifth region while doped n-type in the region adjacent to said third n-type silicon.

17. An inverter comprising:

a first silicon epitaxial region on a first single crystalline substrate having a n-type concentration level greater than 1×

10¹⁹ atoms/cm³,

a second Si_l-i-jGe_iC_j epitaxial region over said first n-type silicon region,

a third silicon epitaxial region over said second Si_l-i-jGe_iC_j epitaxial region doped p-type,

a fourth strained Si_l-yC_y epitaxial region over said third p-type silicon region having a n-type concentration level greater than 1×

10¹⁹ atoms/cm³,

a fifth region selected from a group consisting of single crystalline silicon, poly silicon and poly SiGe over said fourth n-type strained Si_l-yC_y region having a n-type concentration level greater than 1×

10¹⁹ atoms/cm³,

a first vertical structure comprising at least one sidewall extending from said first silicon region, over said second region of strained Si_l-xC_x region, over said third region of p-type silicon, over said fourth region of strained Si_l-yC_y to said fifth region,

a sixth silicon region over a region of said at least one sidewall of said vertical structure,

a first gate dielectric region over said sixth silicon region, and

a first gate conducting region over said gate dielectric region,

a seventh p-type silicon epitaxial region on said first single crystalline substrate having a concentration level greater than 1×

10¹⁹ atoms/cm³,

an eighth carbon-doped epitaxial region over said seventh p-type silicon epitaxial region having a p-type to a concentration level greater than 1×

10¹⁹ atoms/cm³,

a ninth silicon epitaxial region over said eighth carbon-doped epitaxial region doped n-type,

a tenth compressively strained Si_l-w-qGe_wC_q epitaxial region over said ninth silicon epitaxial region having a p-type concentration level greater than 1×

10¹⁹ atom/cm³,

an eleventh region selected from a group consisting of single crystalline silicon, poly silicon and poly SiGe over said tenth Si_l-w-qGe_wC_q region having a p-type concentration level greater than 1×

10¹⁹ atoms/cm³,

a second vertical structure comprising at least one sidewall extending from said seventh p-type silicon region, eighth carbon-doped epitaxial region, ninth silicon epitaxial region, tenth compressively strained Si_l-sGe_wC_q epitaxial region, to said eleventh silicon epitaxial region,

a twelfth strained Si_l-sGe_s region over a region of said at least one sidewall of said vertical structure,

a second gate dielectric region over said twelfth strained Si_l-sGe_s region, and a second gate conducting region over said gate dielectric region.

18. The field effect transistor according to claim 17 further comprising:

a first blanket dielectric layer over and above said first vertical structure,

a first conducting via through said first blanket dielectric layer in contact to said first n-type silicon region,

a second conducting via through said first blanket dielectric layer in contact to said fifth region at the top of said first vertical structure,

a third conducting via through said first blanket dielectric layer in contact to said first gate conducting region,

a second blanket dielectric layer over and above said second vertical structure,

a fourth conducting via through said second blanket dielectric layer in contact to said seventh p-type silicon epitaxial region,

a fifth conducting via through said second blanket dielectric layer in contact to said eleventh p-type silicon containing region at the top of the above vertical structure,

a sixth conducting via through said second blanket dielectric layer in contact to said second gate conducting region, and

a third dielectric region on said first substrate in between said first and second vertical structures to provide device isolation.

19. The inverter according to claim 18 wherein said fourth conducting via is coupled to said first conducting via, said sixth conducting via is coupled to said third conducting via and said fifth conducting via is coupled to said second conducting via by way of conducting material.

20. The inverter according to claim 17 wherein said sidewall of said first vertical structure is in the plane (100), and perpendicular to a major surface of said substrate.

21. The inverter according to claim 17 wherein said sidewall of said second vertical structure is in the plane (110), and perpendicular to a major surface of said substrate.

22. The inverter according to claim 17 wherein said twelfth strained SiGe region is a silicon region.

23. An inverter comprising:

a first relaxed Si_l-iGe_i epitaxial region on a first single crystalline substrate said first Si_l-iGe_i epitaxial layer doped n-type to a concentration level greater than 1×

10¹⁹ atoms/cm³,

a second tensile strained silicon epitaxial region over said first p-type Si_l-iGe_i region, said second silicon epitaxial region doped n-type to a concentration level greater than 1×

10¹⁹ atoms/cm³,

a third relaxed Si_l-iGe_i epitaxial region over said second silicon region, said third silicon epitaxial region doped p-type,

a fourth tensile strained silicon epitaxial region over said third p-type Si_l-iGe_i region, said fourth strained silicon region doped n-type to a concentration level greater than 1×

10¹⁹ atoms/cm³,

a fifth region selected from a group consisting of relaxed Si_l-iGe_i, poly silicon and poly SiGe over said fourth n-type strained silicon region, said fifth Si_l-iGe_i region doped n-type to a concentration level greater than 1×

10¹⁹ atoms/cm³,

a first vertical structure comprising at least one sidewall extending from said first relaxed SiGe region, over said second strained silicon epitaxial region, over said third p-type relaxed Si_l-iGe_i epitaxial region, over said fourth strained silicon epitaxial region to said fifth region,

a sixth strained silicon region over a region of said at least one sidewall of said first vertical structure,

a first gate dielectric region over said sixth silicon region, and

a first gate conducting region over said gate dielectric region,

a seventh p-type silicon epitaxial region on a first single crystalline substrate having a concentration level greater than 1×

10¹⁹ atoms/cm³,

an eighth carbon-doped epitaxial region over said seventh p-type silicon epitaxial region having a p-type to a concentration level greater than 1×

10¹⁹ atoms/cm³,

a ninth silicon epitaxial region over said eighth carbon-doped epitaxial region doped n-type,

a tenth compressively strained Si_l-w-qGe_wC_q epitaxial region over said ninth silicon epitaxial region having a p-type concentration level greater than 1×

10¹⁹ atoms/cm³,

an eleventh region selected from a group consisting of single crystalline silicon, poly Si and poly SiGe over said tenth Si_l-w-qGe_wC_q region having a p-type concentration level greater than 1×

10¹⁹ atoms/cm³,

a second vertical structure comprising at least one sidewall extending from said seventh p-type silicon epitaxial region, eighth carbon-doped epitaxial region, ninth silicon epitaxial region, tenth compressively strained Si_l-w-qGe_wC_q epitaxial region, to said eleventh silicon epitaxial region,

a twelfth strained Si_l-sGe_s region over a region of said at least one sidewall of said second vertical structure,

a second gate dielectric region over said twelfth strained Si_l-sGe_s, region, and

a second gate conducting region over said gate dielectric region.

24. The field effect transistor according to claim 23 further comprising:

a first blanket dielectric layer over and above said first vertical structure,

a first conducting via through said first blanket dielectric layer in contact to said sixth silicon region in the area on top of said first n-type silicon layer,

a second conducting via through said first blanket dielectric layer in contact to said fifth silicon containing region at the top of said first vertical structure,

a third conducting via through said first blanket dielectric layer in contact to said first gate conducting layer,

a second blanket dielectric layer over and above said vertical structure,

a fourth conducting via through said second blanket dielectric layer in contact to said seventh p-type silicon region,

a fifth conducting via through said second blanket dielectric layer in contact to said twelfth strained Si_l-sGe_s region in the area over said eleventh p-type silicon epitaxial region at the top of the above said first vertical structure,

a sixth conducting via through said second blanket dielectric layer in contact to said second gate conducting region, and

a third dielectric region on said first substrate in between said first and second vertical structures to provide device isolation.

25. The inverter according to claim 24 wherein said fourth conducting via is coupled to said first conducting via, said sixth conducting via is coupled to said third conducting via and maid fifth conducting via is coupled to said second conducting via conducting material.

26. The inverter according to claim 23 wherein said sidewall of said first vertical structure is in the plane (100), and perpendicular to a major surface of said substrate.

27. The inverter according to claim 23 wherein said sidewall of said second vertical structure is in the plane (110), and perpendicular to a major surface of said substrate.

28. The inverter according to claim 23 wherein said twelfth strained SiGe region is a silicon region.