Semiconductor device having bridge-connected wiring structure

• US 6,943,445 B2
• Filed: 03/29/2002
• Issued: 09/13/2005
• Est. Priority Date: 03/30/2001
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Fujino, Shinichi, Anan, Hiromichi, Shirakawa, Shinji, Innami, Toshiyuki, Mishima, Akira, Mashino, Keiichi, Ochiai, Yoshitaka
• Primary Examiner(s): Pham, Long
• Assistant Examiner(s): Le, Thao X.
• Application Number:
  US10/468,038
• Publication Number:
  US 20040113268A1
• Time in Patent Office: 1,264 Days
• Field of Search: 257723-724, 257/E23.173, 257/E25.016, 257/718, 257/713, 257/720, 257/E23.084, 257/E23.092, 257/E23.187, 363 55- 56, 363/132, 363/141, 363/144
• US Class Current: 257/724
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/40225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48111 the wire connector extending above another semiconductor or solid-state body
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/49431 on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/49433 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73221 Strap and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/072 the devices being arranged next to each other
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H02M 7/003 : Constructional details, e.g. physical layout, assembly, wiring or busbar connections

Abstract

The present invention provides a semiconductor device which reduces an inductance of wiring for bridge-connecting semiconductor switches and realizes a reduction in size. Within the semiconductor device formed are two controllable bridge-connected semiconductor switches 13a and 13b, an output terminal, positive/negative polarity DC terminals 2 and 3, and an insulating substrate 15a in which conductor layers 12, 17 and 19 having a conductor section and in an inner layer for bridge-connecting the semiconductor switches to the DC terminals on a surface thereof and insulating layers 16 and 18 are alternately laminated. The surface and inner-layer conductor layers 12 and 17 which interpose the insulating layer 16 therebetween are electrically connected by a conductor 20 passing through the insulating layer 16 interposed between the conductor layers 12 and 17. A current path (dotted line) is so provided as to allow current flowing through a bridge circuit for mounting the two semiconductor switches on the insulating substrate to flow in opposite directions between the conductor layers 12 and 17 which interpose the insulating layer 16 therebetween.

Claims

1. A semiconductor device comprising:

at least two controllable semiconductor switches connected in a bridge form;

at least one output terminal;

at least two positive/negative polarity DC terminals; and

an insulating substrate including a conductor section for mounting the semiconductor switches thereon;

wherein the insulating substrate is configured such that at least two conductor layers having a conductor section on a surface thereof and in an inner layer thereof to bridge-connect the semiconductor switches and the DC terminals and at least two insulating layers are alternately laminated,

the surface and inner-layer conductor layers interposing the insulating layer therebetween are electrically connected by a conductor passing through the insulating layer interposed between the conductor layers, and

a current path is so provided as to allow a current flowing through a bridge circuit for mounting said at least two semiconductor switches on the insulating substrate to flow in opposite directions between the conductor layers interposing the insulating layer therebetween.

2. A semiconductor device comprising:

at least two controllable semiconductor switches connected in a bridge form;

at least one output terminal;

at least two positive/negative polarity DC terminals; and

an insulating substrate including a conductor section for mounting the semiconductor switches thereon;

wherein the insulating substrate is configured such that at least two conductor layers having a conductor section on a surface thereof and in an inner layer thereof to bridge-connect the semiconductor switches and the DC terminals and at least two insulating layers are alternately laminated,

the surface and inner-layer conductor layers interposing the insulating layer therebetween are electrically connected by a conductor passing through the insulating layer interposed between the conductor layers,

a current path is so provided as to allow a current flowing through a bridge circuit for mounting said at least two semiconductor switches on the insulating substrate to flow in opposite directions between the conductor layers interposing the insulating layer therebetween, and

a wiring layout is configured in which the semiconductor switches are not mounted on the surface conductor layer connected to the conductor passing through the insulating layer.

3. A semiconductor device comprising:

at least two controllable semiconductor switches connected in a bridge form;

at least one output terminal;

at least two positive/negative polarity DC terminals;

an insulating substrate including a conductor section for mounting the semiconductor switches thereon; and

a radiating plate mounting the insulating substrate thereon;

wherein the insulating substrate is configured such that at least two conductor layers having a conductor section on a surface thereof and in an inner layer thereof to bridge-connect the semiconductor switches and the DC terminals and at least two insulating layers are alternately laminated,

the surface and inner-layer conductor layers interposing the insulating layer therebetween are electrically connected by a conductor passing through the insulating layer interposed between the conductor layers,

a current path is so provided as to allow a current flowing through a bridge circuit for mounting said at least two semiconductor switches on the insulating substrate to flow in opposite directions between the conductor layers interposing the insulating layer therebetween,

a wiring layout is configured in which the semiconductor switches are not mounted on the surface conductor layer connected to the conductor passing through the insulating layer, and

a conductor block is used for a connection between an upper surface of electrode of the semiconductor switch and the surface conductor layer to form a radiation path of the semiconductor switch to the radiation plate.