Apparatus and method for detecting photon emissions from transistors

• US 6,943,572 B2
• Filed: 12/05/2003
• Issued: 09/13/2005
• Est. Priority Date: 09/03/2002
• Status: Expired due to Term

• Current Assignee: DCG Systems Incorporated (Thermo Fisher Scientific Incorporated)
• Original Assignee: Credence Systems Corporation (COHU Incorporated)
• Inventors: Lundquist, Theodore R., Perdu, Philippe, Desplats, Romain, Shah, Ketan J.
• Primary Examiner(s): Nguyen, Vinh
• Assistant Examiner(s): KOBERT, RUSSELL MARC
• Application Number:
  US10/728,522
• Publication Number:
  US 20040189335A1
• Time in Patent Office: 648 Days
• Field of Search: 324751-752, 324/158.1, 250310-312, 716 4- 6
• US Class Current: 324/750.16
• CPC Class Codes: G01R 31/2621 for testing field effect transistors, i.e. FET's
• CPC Class Codes: G01R 31/2846 using hard- or software simulation or using knowledge-based systems, e.g. expert systems, artificial intelligence or interactive algorithms
• CPC Class Codes: G01R 31/311 of integrated circuits G01R31/31728 takes precedence

Abstract

A system, apparatus, and method for analyzing photon emission data to discriminate between photons emitted by transistors and photons emitted by background sources. The analysis involves processing of integrated circuit computer aided design data to identify transistors within the CAD data. The analysis may further involve the use of Boolean operators to process the CAD data to particularly identify, such as through a channel, the location of the NMOS and PMOS gates, the location of the drain and source, or some combination of the location of the gate and drain or source to particularly identify the pinch-off region.

Claims

1. A method for reducing diagnostic time of a photon detecting integrated circuit tester, the method comprising:

processing a CAD database associated with an integrated circuit; and

identifying at least one CAD layer from the CAD database, the at least one CAD layer including at least one photon emission source of the integrated circuit;

processing the at least one CAD layer to determine an expected location of a photon emission source.

2. The method of claim 1 further comprising:

aligning the tester with the at least one CAD layer to correlate the tester with the at least one expected photon emission source.

3. The method of claim 2 further comprising:

identifying photon emissions from the at least one expected photon emission source, the photon emissions detected by the tester during operation of the integrated circuit.

4. The method of claim 3 wherein the operation of identifying photon emissions from the at least one expected photon emission source comprises receiving photon emission through the a semiconductor substrate of the integrated circuit.

5. The method of claim 3 wherein the photon emissions detected by the tester during operation of the integrated circuit in a test loop.

6. The method of claim 3 further comprising:

determining at least one operating characteristic of the at least one expected photon emission source.

7. The method of claim 6 wherein the operation of determining the at least one operating characteristic comprises determining timing measurements employing a single photon counting technique.

8. The method of claim 7 further comprising:

comparing the at least one operating characteristic of the at least one expected photon emission source with a simulation of the operating integrated circuit.

9. The method of claim 8 wherein the simulation is in an optical waveform format.

10. The method of claim 8 wherein the simulation is in a voltage level format.

11. The method of claim 6 wherein the at least one expected emission source is at least one transistor.

12. The method of claim 11 wherein the operation of comparing the operating characteristics of the least one transistor includes identifying transistors that are and are not working in accordance with the simulation.

13. The method of claim 11 wherein the operation of comparing the operating characteristics of the least one transistor includes identifying emission peaks of transistors that are or are not present in the simulation.

14. The method of claim 11 wherein the operation of comparing the operating characteristics of the least one transistor includes identifying differences between operating characteristics of the at least one expected photon emission source and the simulation.

15. The method of claim 11 wherein the operation of determining the at least one operating characteristic of the at least one expected photon emission source comprises determining a commutation timing of the at least one transistor.

16. The method of claim 1 wherein the at least one expected emission source is a MOS device.

17. The method of claim 1 wherein the at least one expected emission source is a PMOS device.

18. The method of claim 1 wherein the at least one expected emission source is a NMOS device.

19. The method of claim 1 wherein the at least one expected emission source is a nFET.

20. The method of claim 1 wherein the at least one expected emission source is a pFET.

21. The method of claim 1 wherein the tester comprises an optical detector.

22. The method of claim 1 wherein the tester comprises a laser scanning microscope.

23. The method of claim 1 wherein the tester comprises a picosecond imaging circuit analysis detector.

24. The method of claim 1 wherein the tester comprises a static emission detector.

25. The method of claim 1 wherein the tester comprises a superconducting single photon detector.