Multichip package test

• US 6,943,577 B2
• Filed: 10/01/2003
• Issued: 09/13/2005
• Est. Priority Date: 10/01/2002
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kwon, Hyuk, Shim, Hyun-Seop, Lee, Hyoung-Young, Shin, Young-Gu, Heo, Kyoung-Il, Ju, Ki-Bong, Bang, Jeong-Ho
• Primary Examiner(s): KARLSEN, ERNEST F
• Application Number:
  US10/677,743
• Publication Number:
  US 20040119491A1
• Time in Patent Office: 713 Days
• Field of Search: 324/537, 324/754, 324/760, 324/765, 714/718, 714/724
• US Class Current: 324/762.06
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/318513 Test of Multi-Chip-Moduls

Abstract

A test apparatus for testing a multi-chip package comprising a multiplicity of semiconductor chips, which includes a test driver having one drive channel and at least one input/output channel. A test board is mounted with the multi-chip package. Drive pins of the semiconductor chips are parallel connected to the drive channel, and input/output pins of the semiconductor chips are parallel connected to the input/output channel.

Claims

1. A method of testing a package mounted with a plurality of semiconductor chips, comprising:

connecting a drive channel of a test driver to a plurality of drive pins corresponding to the plurality of semiconductor chips;

connecting an input/output channel of a test driver to a plurality of input/output pins corresponding to the plurality of semiconductor chips; and

setting, while one of the semiconductor chips is being tested, the drive and input/output pins of other semiconductor chips to a high impedance state.

2. The method of claim 1 where the drive pins include control and address pins.