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Variable fixed multipliers using memory blocks

  • US 6,943,579 B1
  • Filed: 09/22/2003
  • Issued: 09/13/2005
  • Est. Priority Date: 12/20/2002
  • Status: Expired due to Fees
First Claim
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1. A programmable logic device comprising:

  • at least one RAM block generating at least a first multi-bit calculation result;

    a shift operation driven by a second multi-bit calculation result and that shifts the second multi-bit calculation result by at least one bit to generate a shifted second multi-bit calculation result; and

    a multi-bit adder coupled to the at least one RAM block and which adds the shifted second multi-bit calculation result to the first multi-bit calculation result.

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