Variable fixed multipliers using memory blocks
First Claim
Patent Images
1. A programmable logic device comprising:
- at least one RAM block generating at least a first multi-bit calculation result;
a shift operation driven by a second multi-bit calculation result and that shifts the second multi-bit calculation result by at least one bit to generate a shifted second multi-bit calculation result; and
a multi-bit adder coupled to the at least one RAM block and which adds the shifted second multi-bit calculation result to the first multi-bit calculation result.
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Abstract
A programmable logic device includes at least one RAM block generating a first multi-bit calculation result which may, but does not necessarily, involve a multiplication of two operands. A shift operation is driven by a second multi-bit calculation result shifts the second multi-bit calculation result by at least one bit to generate a shifted second multi-bit calculation result. A multi-bit adder coupled to the at least one RAM block adds the shifted second multi-bit calculation result to the first multi-bit calculation result.
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Citations
39 Claims
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1. A programmable logic device comprising:
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at least one RAM block generating at least a first multi-bit calculation result; a shift operation driven by a second multi-bit calculation result and that shifts the second multi-bit calculation result by at least one bit to generate a shifted second multi-bit calculation result; and a multi-bit adder coupled to the at least one RAM block and which adds the shifted second multi-bit calculation result to the first multi-bit calculation result. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A programmable logic device comprising:
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at least one RAM block configured with at least one LUT for generating at least a first multi-bit multiplication result; a shift operation driven by a second multi-bit multiplication result and that shifts the second multi-bit multiplication result by at least one bit to generate a shifted second multi-bit multiplication result; and an adder having a first input and a second input wherein the first input is driven by the first multi-bit multiplication result and the second input is driven by the shifted second multi-bit multiplication result, the adder adding the first multi-bit multiplication result to the second shifted multi-bit multiplication result. - View Dependent Claims (22, 23, 24)
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25. A method of carrying out a multi-bit calculation including:
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inputting at least a first multi-bit word into at least one RAM block configured with at least one LUT; generating at least a first multi-bit calculation result from the at least one LUT in the at least one RAM block; generating at least a second multi-bit calculation result; shifting the at least second multi-bit calculation result by at least one bit to generate a shifted second multi-bit calculation result; and adding the shifted second multi-bit calculation result to the first multi-bit calculation result. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39)
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Specification