Fracturable lookup table and logic element

• US 6,943,580 B2
• Filed: 02/10/2003
• Issued: 09/13/2005
• Est. Priority Date: 02/10/2003
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Kaptanoglu, Sinan, Lewis, David, Pedersen, Bruce, Lee, Andy
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): NGUYEN, KHAI M
• Application Number:
  US10/364,310
• Publication Number:
  US 20040155677A1
• Time in Patent Office: 946 Days
• Field of Search: 326 37- 41, 326/105
• US Class Current: 326/40
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables

Abstract

A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.

Claims

1. A logic element comprising:

a plurality of memory elements;

a plurality of multiplexers arranged in a plurality of levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output, at least two same-level multiplexers having inputs that are connected to a shared output of a higher-level multiplexer; and

a plurality of controls connected to the multiplexers, wherein

in a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexer, and

in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.

2. A logic element as claimed in claim 1, wherein in the first operational mode, the first-mode output provides a complete function of the controls.

3. A logic element as claimed in claim 2, wherein in the second operational mode, each second-mode output provides a complete function of a proper subset of the controls.

4. A logic element as claimed in claim 3, wherein in the second operational mode each control belongs to at least one of the proper subsets for which the second-mode outputs provide complete functions.

5. A logic element as claimed in claim 1, wherein in the second operational mode, one or more controls are split into a plurality of sub-controls so that a corresponding sub-control replaces each split control at each multiplexer connected to that split control.

6. A logic element as claimed in claim 1, further comprising:

one or more control multiplexers with outputs connected to one or more of the controls and with inputs determined by a plurality of control-multiplexer inputs.

7. A logic element as claimed in claim 6, further comprising

one or more input-output multiplexers with inputs connected to one or more input, of the multiplexers and one or more outputs of the multiplexers arranged in levels.

8. A logic element as claimed in claim 7, wherein at least two of the control-multiplexers receive an identical control-multiplexer input.

9. A logic element as claimed in claim 7, further comprising:

one or more flip-flops with inputs connected to one or more inputs of the control multiplexers.

10. A logic element as claimed in claim 7, further comprising:

one or more flip-flops with inputs connected to one or more outputs of the input-output multiplexers.

11. A logic element as claimed in claim 1, further comprising:

one or more mode multiplexers connected to the logic element for switching between the first operational mode and the second operational mode.

12. A programmable logic device, comprising:

a logic element according to claim 1.

13. A data processing system, comprising:

a programmable logic device according to claim 12.

14. A logic element as claimed in claim 1, wherein the common control connects to each multiplexer in the highest level of multiplexers.

15. A logic element as claimed in claim 1, wherein the controls include at least one common control connected to each multiplexer in a level that includes plural multiplexers.

16. A method of making a logic element, comprising:

providing a plurality of memory elements;

providing a plurality of multiplexers, the multiplexers being arranged in a plurality of levels including a highest level of multiplexes with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output, and at least two same-level multiplexers having inputs that are connected to a shared output of a higher-level multiplexer; and

providing a plurality of controls, the controls being connected to the multiplexers, including at least one common control connected to each multiplexer in a level that includes plural multiplexers, wherein

in a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and

in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.

17. A method an claimed in claim 16, wherein in the first operational mode, the first-mode output provides a complete function of the controls.

18. A method as claimed in claim 17, wherein in the second operational mode, each second-mode output provides a complete function of a proper subset of the controls.

19. A method as claimed in claim 18, wherein in the second operational mode each control belongs to at least one of the proper subsets for which the second-mode outputs provide complete functions.

20. A method as claimed in claim 16, wherein in the second operational mode, one or more controls are split into a plurality of sub-controls so that a corresponding sub-control replaces each split control at each multiplexer connected to that split control.

21. A method as claimed in claim 16, further comprising:

adding to the logic element one or more control multiplexers with outputs connected to one or more of the controls of the logic element and with inputs determined by a plurality of control-multiplexer inputs.

22. A method as claimed in claim 21, further comprising:

adding to the logic element one or more input-output a multiplexers with inputs connected to one or more inputs of the control multiplexers and one or more outputs of the multiplexers arranged in levels.

23. A method as claimed in claim 22, wherein at least two of the control-multiplexers receive an identical control-multiplexer input.

24. A method as claimed in claim 22, further comprising:

adding to the logic element one or more flip-flops with inputs connected to one or more inputs of the control multiplexers.

25. A method an claimed in claim 22, farther comprising:

adding to the logic element one or more flip-flops with inputs connected to one or more outputs of the input-output multiplexers.

26. A method as claimed in claim 16, further comprising:

adding to the logic element one or more mode multiplexers connected to the logic element for switching between the first operational mode and the second operational mode.

27. A method as claimed in claim 16, wherein the common control connects to each multiplexer in the highest level of multiplexers.

28. A method as claimed in claim 16, wherein at least two same-level multiplexers have inputs that are connected to a shared output of a higher-level multiplexer.

29. A logic element comprising;

a plurality of memory elements;

a plurality of multiplexers arranged in a plurality of levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output at least two same-level multiplexers having inputs that are connected to a shared output of a higher-level multiplexer and

a plurality of controls connected to the multiplexers, including at least one common control connected to each multiplexer in a level that includes plural multiplexers;

one or more control multiplexers with outputs connected to one or more of the controls and with inputs determined by a plurality of control-multiplexer inputs; and

one or more mode multiplexers for switching between the first operational mode and the second operational mode, wherein

in a first operational mode the controls determine a first-mode, output at the at least one output of the first level of multiplexers, and

in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.

30. A programmable logic device, comprising:

a logic element according to claim 29.

31. A data processing system, comprising:

a programmable logic device according to claim 30.

32. A logic element comprising:

a plurality of memory elements;

a plurality of multiplexers arranged in a plurality of levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output, at least two same-level multiplexers having inputs that are connected to shared outputs of higher-level multiplexers so that each input of the at least two same-level multiplexers is connected to a shared output; and

a plurality of controls connected to the multiplexers, wherein

in a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and

in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.

33. A logic element comprising:

a plurality of memory elements;

a plurality of multiplexers arranged in a plurality of levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output, multiplexers of a shared-output level having inputs that are connected to shared outputs of higher-level multiplexers so that each input of the multiplexers of the shared-output level is connected to a shared output; and

a plurality of controls connected to the multiplexers, wherein

in a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and

in a second operational made the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.

34. A method of making a logic element, comprising:

providing a plurality of memory elements;

providing a plurality of multiplexers, the multiplexers being arranged in a plurality of levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs oh next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output, and at least two same-level multiplexers having inputs that are connected to shared outputs of higher-level multiplexers so that each input of the at least two same-level multiplexers is connected to a shared output; and

providing a plurality of controls, the controls being connected to the multiplexers,

wherein

in a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and

in a second operational mode the controls determine a plurality of second-mode outputs at selected, outputs of multiplexers not at the first level of multiplexers.

35. A method of making a logic element, comprising:

providing a plurality of memory element;

providing a plurality of multiplexers, the multiplexers being arranged in a plurality of levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-higher level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output, multiplexers of a shared-output level having inputs that are connected to shared outputs of higher-level multiplexers so that each input of the multiplexers of the shared-output level is connected to a shared output; and

providing a plurality of controls, the controls being connected to the multiplexers,

wherein

in a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and

in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.