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Clock distribution network using feedback for skew compensation and jitter filtering

  • US 6,943,610 B2
  • Filed: 04/19/2002
  • Issued: 09/13/2005
  • Est. Priority Date: 04/19/2002
  • Status: Expired due to Fees
First Claim
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1. An architecture for clock distribution on an integrated circuit (IC), comprising:

  • a clock distribution network;

    a plurality of clock processor nodes distributed throughout the clock distribution network on the IC at respective local clock regions; and

    a master clock generator to generate a master clock for distribution to the clock processor nodes, via the clock distribution network, to compensate clock skew and filter clock jitter locally at the respective local clock regions; and

    wherein;

    the master clock generator corresponds to a master phase-locked loop (PLL) to generate and keep the master clock synchronized responsive to a system clock; and

    each clock processor node at each local clock region comprises;

    a slave phase-locked loop (PLL) to attenuate the clock jitter from the master clock introduced by the clock distribution network; and

    a variable-delay element (VDE) to compensate the clock skew from the master clock introduced by the clock distribution network.

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