Method and apparatus of obtaining power computation parameters

• US 6,943,714 B2
• Filed: 08/07/2003
• Issued: 09/13/2005
• Est. Priority Date: 08/19/2002
• Status: Active Grant

• Current Assignee: Silergy Semiconductor (Samoa) Ltd. (Silergy Corporation)
• Original Assignee: TDK Semiconductor Corporation (Analog Devices, Inc.)
• Inventors: White, Bert
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Nguyen, Linh V
• Application Number:
  US10/637,969
• Publication Number:
  US 20040032357A1
• Time in Patent Office: 768 Days
• Field of Search: 341/110, 341/118, 341/120, 341/141, 341/143, 341/155
• US Class Current: 341/141
• CPC Class Codes: G01R 21/133 by using digital technique

Abstract

A method and apparatus for obtaining power computation parameters is presented. Accurate computation of power requires multiplying voltage and current at the same instant of time and integrating the results over time. The present invention provides a method of using a single Analog to Digital Converter to convert both voltage and current for all the phases of any electrical system and then digitally compensating for the phase error caused by the non-simultaneous sampling of the current and voltage signals. The compensating filter could be implemented as a simple interpolator, an all-pass filter, or a combination of both. A single multiplexer is used to select which signal is processed by the Analog to Digital Converter. By scheduling and converting the voltage and analog signals one at a time, potential for crosstalk is significantly reduced, power requirement is reduced, and die size requirement is reduced.

Claims

1. A method for obtaining power computation parameters comprising:

generating a single analog signal from a plurality of multi-phase analog signals, wherein said single analog signal takes on a value of one of said plurality of multi-phase analog signals at each cycle of a first clock signal;

converting said single analog signal to a digital representation using a second clock signal;

generating a plurality of digital signals from said digital representation, wherein each one of said plurality of digital signals represents a digital form of one of said plurality of multi-phase analog signals; and

obtaining power computation parameters by compensating said plurality of digital signals for differences in sample interval thereby providing digital values of all signals in each phase of said plurality of multi-phase analog signals at the same sample time.

2. The method of claim 1, wherein said compensating said plurality of digital signals comprises computing equivalent digital values at the same clock time for all analog signals in each phase of said plurality of multi-phase analog signals.

3. The method of claim 2, wherein said computing equivalent digital values comprises passing an appropriate one of said plurality of digital signals from each of said phase through an interpolation filter.

4. The method of claim 2, wherein said computing equivalent digital values comprises applying a high order interpolation circuit to an appropriate one of said plurality of digital signals in each of said phase.

5. The method of claim 2, wherein said computing equivalent digital values comprises passing an appropriate one of said plurality of digital signals from each of said phase through an an allpass filter.

6. The method of claim 1, wherein said converting said single analog signal comprises using oversampling techniques to convert said analog signal to said digital representation.

7. The method of claim 1, wherein said first clock signal is an integer multiple of said second clock signal.

8. A method for computing power comprising:

selecting a first analog signal from two analog signals comprising a current signal and a voltage signal;

converting said first analog signal to a first digital representation using an analog to digital converter at a first sample interval;

making said first digital representation available as a first digital signal;

selecting a second analog signal of said two analog signals;

converting said second analog signal to a second digital representation using said analog to digital converter at a second sample interval;

computing a second digital signal representing said second analog signal at said first sample interval using said second digital representation; and

computing electrical power consumption using said first digital signal and said second digital signal.

9. The method of claim 8, wherein said computing said second digital signal comprises using said second digital representation at said second sample interval and at least one previous sample of said second digital representation in an interpolation filter.

10. The method of claim 8, wherein said computing said second digital signal comprises using said second digital representation at said second sample interval and a plurality of previous samples of said second digital representation in a high order polynomial interpolator.

11. The method of claim 8, wherein said computing said second digital signal comprises passing said second digital representation through an allpass filter.

12. An apparatus for obtaining power computation parameters comprising:

a multiplexer for generating a single analog signal from a plurality of multi-phase analog signals, wherein said single analog signal takes on a value of one of said plurality of multi-phase analog signals at each cycle of a first clock signal;

an analog to digital converter converting said single analog signal to a digital representation using a second clock signal;

a demultiplexing device generating a plurality of digital signals from said digital representation, wherein each one of said plurality of digital signals represents a digital form of one of said plurality of multi-phase analog signals; and

a phase correction circuit compensating said plurality of digital signals for sample skew associated with said converting in said analog to digital converter to obtain digital samples values at the same sample interval, wherein said phase correction circuit is not a phase delay.

13. The apparatus of claim 12, wherein said compensating said plurality of digital signals comprises computing equivalent digital values at the same clock time for all analog signals in each phase of said plurality of multi-phase analog signals.

14. The apparatus of claim 13, wherein said computing equivalent digital values comprises passing an appropriate one of said plurality of digital signals from each of said phase through an interpolation filter.

15. The apparatus of claim 13, wherein said computing equivalent digital values comprises applying a high order interpolation circuit to an appropriate one of said plurality of digital signals in each of said phase.

16. The apparatus of claim 13, wherein said computing equivalent digital values comprises passing an appropriate one of said plurality of digital signals from each of said phase through an allpass filter.

17. The apparatus of claim 12, wherein said analog to digital converter uses oversampling techniques to convert said analog signal to said digital representation.

18. The apparatus of claim 12, wherein said analog to digital converter is a delta-sigma converter.

19. The apparatus of claim 12, wherein said first clock signal is an integer multiple of said second clock signal.

20. An apparatus for computing power comprising:

a multiplexer selecting a first analog signal from two analog signals at a first sample interval, said multiplexer selecting a second analog signal of said two analog signals at a second sample interval;

an analog to digital converter converting said first analog signal to a first digital representation at said first sample interval, said analog to digital converter converting said second analog signal to a second digital representation at said second sample interval;

a demultiplexing device parsing said first digital representation as a first digital signal said second digital representation as a second digital signal; and

a power computation circuitry having a phase correction circuit for generating a third digital signal representing a digital equivalent value of said second analog signal at said first sample interval using said second digital signal, said power computation circuitry computing electrical power consumption using said first digital signal and said third digital signal.

21. The apparatus of claim 20, wherein said two analog signals comprise a current signal and a voltage signal.

22. The apparatus of claim 20, wherein each of said two analog signals has a plurality of corresponding phases.

23. The apparatus of claim 22, wherein each of said plurality of corresponding phases are sampled in order.

24. The apparatus of claim 20, wherein said phase correction circuit is an interpolation filter comprising digital circuit using said second digital representation at said second sample interval and at least one previous sample of said second digital representation.

25. The apparatus of claim 20, wherein said phase correction circuit is a high order polynomial interpolator comprising digital circuit using said second digital representation at said second sample interval and a plurality of previous samples of said second digital representation.

26. The apparatus of claim 20, wherein said phase correction circuit is an allpass filter comprising digital circuit using said second digital representation.

27. The apparatus of claim 20, wherein said analog to digital converter is a delta-sigma converter.