Low voltage data path and current sense amplifier

• US 6,944,066 B1
• Filed: 04/29/2004
• Issued: 09/13/2005
• Est. Priority Date: 04/29/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jing, Chul Min
• Primary Examiner(s): Auduong, Gene N.
• Application Number:
  US10/835,704
• Time in Patent Office: 502 Days
• Field of Search: 365/189.01, 365/189.05, 365/189.11, 365/205, 365/207
• US Class Current: 365/189.05
• CPC Class Codes: G11C 2207/063 Current sense amplifiers
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

A data path including a local input/output (LIO) line and a global input/output (GIO) line coupled together through an input/output (IO) line coupling circuit. The coupling circuit is coupled to an internal voltage supply, and couples and decouples signal lines of the GIO line from the supply terminal according to read data coupled to the LIO line. The GIO line is coupled to a current sense amplifier to generate output voltage signals that are coupled to an output buffer. An example of a current sense amplifier coupled to the GIO line includes first and second load circuits and first and second n-channel MOS (NMOS) transistors coupled to a respective load circuit. The gates of NMOS transistors are cross coupled, and input current signals are coupled to source terminals of the NMOS transistors and the output voltage signals are coupled from the drain terminals of the NMOS transistors.

Claims

1. A data path coupled to a read/write circuit for coupling data from the read/write circuit to an output buffer, the data path comprising:

a local input/output (LIO) line coupled to the read/write circuit, the LIO having first and second signal lines to which complementary data from the read/write circuit are coupled;

an input/output (IO) line coupling circuit having first and second control terminals coupled to the first and second signal lines of the LIO line, respectively, a supply terminal coupled to an internal voltage supply, and first and second output nodes to which the supply terminal is coupled and from which the supply terminal is decoupled according to the complementary data coupled to the first and second signal lines of the LIO line, respectively;

a global input/output (GIO) line having first and second signal lines coupled to the first and second output terminals of the IO line coupling circuit; and

an output data amplifier coupled to the first and second signal lines of the GIO line and adapted to generate complementary output voltage signals at output terminals coupled to the output buffer based on input currents coupled over the GIO line to the output data amplifier.

2. The data path of claim 1 wherein the IO line coupling circuit comprises:

first and second p-channel MOS (PMOS) transistors, each having a source terminal coupled to the internal voltage supply, a gate terminal to which a selection signal is applied, and a drain terminal; and

first and second n-channel MOS (NMOS) transistors, each having a drain terminal coupled to a drain terminal of a respective PMOS transistor, a gate terminal coupled to a respective signal line of the LIO line, and a source terminal coupled to a respective signal line of the GIO line.

3. The data path of claim 1 wherein the output data amplifier is a current sense amplifier.

4. The data path of claim 3 wherein the current sense amplifier comprises:

first and second load circuits, each load circuit having a first terminal coupled to an internal voltage supply and further having a second terminal;

first and second n-channel MOS (NMOS) transistors, each NMOS transistor having a drain terminal coupled to the second terminal of a respective load circuit and further coupled to the output buffer to provide the complementary output voltage signals, a gate terminal coupled to the drain terminal of the other NMOS transistor, and a source terminal coupled to a respective signal line of the GIO line to receive the input current signals; and

a precharge circuit coupled to the source terminals of the first and second NMOS transistors and adapted to couple the source terminals to a ground to prepare the current sense amplifier for sensing.

5. The data path of claim 4 wherein the precharge circuit comprises first and second precharge transistors, each having a drain coupled to the source of a respective NMOS transistor, a gate terminal to which a precharge activation signal is applied, and a source coupled to ground.

6. The data path of claim 1, further comprising:

first and second precharge transistors coupled to the first and second signal lines of the LIO line, respectively, to couple the respective signal line to the internal voltage supply in response to an active precharge signal; and

a balancing transistor coupled to the first and second signal lines of the LIO line to couple the same together in response to the active precharge signal.

7. A current sense amplifier for generating complementary output voltage signals in response to input current signals, the current sense amplifier comprising:

first and second load circuits, each load circuit having a first terminal coupled to an internal voltage supply and further having a second terminal;

first and second n-channel MOS (NMOS) transistors, each NMOS transistor having a drain terminal coupled to the second terminal of a respective load circuit, a gate terminal coupled to the drain terminal of the other NMOS transistor, and a source terminal, the input current signals coupled to the source terminals of the NMOS transistors and the complementary output voltage signals coupled from the drain terminals of the NMOS transistors; and

a precharge circuit coupled to the source terminals of the first and second NMOS transistors and adapted to couple the source terminals to a ground to prepare the current sense amplifier for sensing.

8. The current sense amplifier of claim 7 wherein the precharge circuit comprises first and second precharge transistors, each having a drain coupled to the source of a respective NMOS transistor, a gate terminal to which a precharge activation signal is applied, and a source coupled to ground.

9. The current sense amplifier of claim 7 wherein the first and second load circuits comprise resistive load devices.

10. The current sense amplifier of claim 7 wherein the first and second load circuits comprises first and second p-channel MOS (PMOS) transistors, each having a source terminal coupled to the internal voltage supply, a gate coupled to ground, and a drain terminal coupled to the drain of a respective NMOS transistor.

11. A data path coupled to a read/write circuit for coupling data from the read/write circuit to an output buffer, the data path comprising:

a local input/output (LIO) line coupled to the read/write circuit, the LIO having first and second signal lines to which complementary data from the read/write circuit are coupled;

an input/output (IO) line coupling circuit having first and second control terminals coupled to the first and second signal lines of the LIO line, respectively, a supply terminal coupled to an internal voltage supply, and first and second output nodes to which the supply terminal is coupled and from which the supply terminal is decoupled according to the complementary data coupled to the first and second signal lines of the LIO line, respectively;

a global input/output (GIO) line having first and second signal lines coupled to the first and second output terminals of the IO line coupling circuit; and

a current sense amplifier for generating complementary output voltage signals in response to input current signals, the current sense amplifier including first and second load circuits, each load circuit having a first terminal coupled to an internal voltage supply and further having a second terminal, and including first and second n-channel MOS (NMOS) transistors, each NMOS transistor having a drain terminal coupled to the second terminal of a respective load circuit and further coupled to the output buffer to provide the complementary output voltage signals, a gate terminal coupled to the drain terminal of the other NMOS transistor, and a source terminal coupled to a respective signal line of the GIO line to receive the input current signals, the current sense amplifier further including a precharge circuit coupled to the source terminals of the first and second NMOS transistors and adapted to couple the source terminals to a ground to prepare the current sense amplifier for sensing.

12. The data path of claim 11 wherein the IO line coupling circuit comprises:

first and second p-channel MOS (PMOS) transistors, each having a source terminal coupled to the internal voltage supply, a gate terminal to which a selection signal is applied, and a drain terminal; and

first and second n-channel MOS (NMOS) transistors, each having a drain terminal coupled to a drain terminal of a respective PMOS transistor, a gate terminal coupled to a respective signal line of the LIO line, and a source terminal coupled to a respective signal line of the GIO line.

13. The data path of claim 11, further comprising:

first and second precharge transistors coupled to the first and second signal lines of the LIO line, respectively, to couple the respective signal line to the internal voltage supply in response to an active precharge signal; and

a balancing transistor coupled to the first and second signal lines of the LIO line to couple the same together in response to the active precharge signal.

14. The data path of claim 11 wherein the output data amplifier is a current sense amplifier.

15. The data path of claim 14 wherein the current sense amplifier comprises:

first and second load circuits, each load circuit having a first terminal coupled to an internal voltage supply and further having a second terminal;

first and second n-channel MOS (NMOS) transistors, each NMOS transistor having a drain terminal coupled to the second terminal of a respective load circuit and further coupled to the output buffer to provide the complementary output voltage signals, a gate terminal coupled to the drain terminal of the other NMOS transistor, and a source terminal coupled to a respective signal line of the GIO line to receive the input current signals; and

a precharge circuit coupled to the source terminals of the first and second NMOS transistors and adapted to couple the source terminals to a ground to prepare the current sense amplifier for sensing.

16. The data path of claim 15 wherein the precharge circuit comprises first and second precharge transistors, each having a drain coupled to the source of a respective NMOS transistor, a gate terminal to which a precharge activation signal is applied, and a source coupled to ground.

17. The data path of claim 15 wherein the first and second load circuits of the current sense amplifier comprise resistive load devices.

18. The data path of claim 15 wherein the first and second load circuits of the current sense amplifier comprises first and second p-channel MOS (PMOS) transistors, each having a source terminal coupled to the internal voltage supply, a gate coupled to ground, and a drain terminal coupled to the drain of a respective NMOS transistor.

19. A memory device comprising:

an address bus;

a control bus;

an address decoder coupled to the address bus;

a control circuit coupled to the control bus;

a memory-cell array coupled to the address decoder and control circuit

a read/write circuit coupled to the memory-cell array;

an output data buffer; and

a data path coupled to a read/write circuit and the output data buffer for coupling data from the read/write circuit to the output data buffer, the data path comprising;

a local input/output (LIO) line coupled to the read/write circuit, the LIO having first and second signal lines to which complementary data from the read/write circuit are coupled;

an input/output (IO) line coupling circuit having first and second control terminals coupled to the first and second signal lines of the LIO line, respectively, a supply terminal coupled to an internal voltage supply, and first and second output nodes to which the supply terminal is coupled and from which the supply terminal is decoupled according to the complementary data coupled to the first and second signal lines of the LIO line, respectively;

a global input/output (GIO) line having first and second signal lines coupled to the first and second output terminals of the IO line coupling circuit; and

an output data amplifier coupled to the first and second signal lines of the GIO line and adapted to generate complementary output voltage signals at output terminals coupled to the output data buffer based on input currents coupled over the GIO line to the output data amplifier.

20. The memory device of claim 19 wherein the IO line coupling circuit of the data path comprises:

first and second p-channel MOS (PMOS) transistors, each having a source terminal coupled to the internal voltage supply, a gate terminal to which a selection signal is applied, and a drain terminal; and

first and second n-channel MOS (NMOS) transistors, each having a drain terminal coupled to a drain terminal of a respective PMOS transistor, a gate terminal coupled to a respective signal line of the LIO line, and a source terminal coupled to a respective signal line of the GIO line.

21. The memory device of claim 19 wherein the output data amplifier of the data path is a current sense amplifier.

22. The memory device of claim 21 wherein the current sense amplifier of the data path comprises:

first and second load circuits, each load circuit having a first terminal coupled to an internal voltage supply and further having a second terminal;

first and second n-channel MOS (NMOS) transistors, each NMOS transistor having a drain terminal coupled to the second terminal of a respective load circuit and further coupled to the output buffer to provide the complementary output voltage signals, a gate terminal coupled to the drain terminal of the other NMOS transistor, and a source terminal coupled to a respective signal line of the GIO line to receive the input current signals; and

a precharge circuit coupled to the source terminals of the first and second NMOS transistors and adapted to couple the source terminals to a ground to prepare the current sense amplifier for sensing.

23. The memory device of claim 22 wherein the precharge circuit comprises first and second precharge transistors, each having a drain coupled to the source of a respective NMOS transistor, a gate terminal to which a precharge activation signal is applied, and a source coupled to ground.

24. The memory device of claim 19 wherein the data path further comprises:

first and second precharge transistors coupled to the first and second signal lines of the LIO line, respectively, to couple the respective signal line to the internal voltage supply in response to an active precharge signal; and

a balancing transistor coupled to the first and second signal lines of the LIO line to couple the same together in response to the active precharge signal.

25. A processor-based system, comprising:

a data input device;

a data output device;

a processor coupled to the data input and output devices; and

a memory device coupled to the processor, the memory device comprising;

an address bus;

a control bus;

an address decoder coupled to the address bus;

a control circuit coupled to the control bus;

a memory-cell array coupled to the address decoder and control circuit

a read/write circuit coupled to the memory-cell array;

an output data buffer; and

a data path coupled to a read/write circuit and the output data buffer for coupling data from the read/write circuit to the output data buffer, the data path comprising;

a local input/output (LIO) line coupled to the read/write circuit, the LIO having first and second signal lines to which complementary data from the read/write circuit are coupled;

an input/output (IO) line coupling circuit having first and second control terminals coupled to the first and second signal lines of the LIO line, respectively, a supply terminal coupled to an internal voltage supply, and first and second output nodes to which the supply terminal is coupled and from which the supply terminal is decoupled according to the complementary data coupled to the first and second signal lines of the LIO line, respectively;

a global input/output (GIO) line having first and second signal lines coupled to the first and second output terminals of the IO line coupling circuit; and

an output data amplifier coupled to the first and second signal lines of the GIO line and adapted to generate complementary output voltage signals at output terminals coupled to the output data buffer based on input currents coupled over the GIO line to the output data amplifier.

26. The processor-based system of claim 25 wherein the IO line coupling circuit of the data path comprises:

first and second p-channel MOS (PMOS) transistors, each having a source terminal coupled to the internal voltage supply, a gate terminal to which a selection signal is applied, and a drain terminal; and

first and second n-channel MOS (NMOS) transistors, each having a drain terminal coupled to a drain terminal of a respective PMOS transistor, a gate terminal coupled to a respective signal line of the LIO line, and a source terminal coupled to a respective signal line of the GIO line.

27. The processor-based system of claim 25 wherein the output data amplifier of the data path is a current sense amplifier.

28. The processor-based system of claim 27 wherein the current sense amplifier of the data path comprises:

first and second load circuits, each load circuit having a first terminal coupled to an internal voltage supply and further having a second terminal;

first and second n-channel MOS (NMOS) transistors, each NMOS transistor having a drain terminal coupled to the second terminal of a respective load circuit and further coupled to the output buffer to provide the complementary output voltage signals, a gate terminal coupled to the drain terminal of the other NMOS transistor, and a source terminal coupled to a respective signal line of the GIO line to receive the input current signals; and

a precharge circuit coupled to the source terminals of the first and second NMOS transistors and adapted to couple the source terminals to a ground to prepare the current sense amplifier for sensing.

29. The processor-based system of claim 28 wherein the precharge circuit comprises first and second precharge transistors, each having a drain coupled to the source of a respective NMOS transistor, a gate terminal to which a precharge activation signal is applied, and a source coupled to ground.

30. The processor-based system of claim 25 wherein the data path further comprises:

first and second precharge transistors coupled to the first and second signal lines of the LIO line, respectively, to couple the respective signal line to the internal voltage supply in response to an active precharge signal; and

a balancing transistor coupled to the first and second signal lines of the LIO line to couple the same together in response to the active precharge signal.

31. A method of coupling data from a read/write circuit to an output buffer, comprising:

coupling first and second signal lines of a global input/output line to an internal voltage supply;

coupling read data to first and second signal lines of a local input/output line;

decoupling the first or second signal lines of the global input/output line from the internal voltage supply based on the read data coupled to the signal lines of the local input/output line;

sensing a current difference between the first and second signal lines of the global input/output lines after decoupling; and

generating an output voltage signal based on the current difference to provide to the output buffer.

32. The method of claim 31 wherein coupling first and second signal lines of a global input/output line to an internal voltage supply comprise activating first and second pairs of transistors, each pair coupled in series between the internal voltage supply and a respective signal line of the global input/output line.

33. The method of claim 32 wherein decoupling the first or second signal lines of the global input/output line from the internal voltage supply based on the read data coupled to the signal lines of the local input/output line comprises deactivating one of the pair of transistors of either the first or second pairs of transistors in response to the coupling of the read data to the first and second signal lines.

34. The method of claim 33, further comprising precharging the first and second signal lines of the local input/output line to a precharge voltage level.

35. The method of claim 34 wherein precharging the first and second signal lines of the local input/output line to a precharge voltage level comprising coupling the first and second signal lines of the local input/output line to the inter voltage supply.

36. A method of coupling read data from first and second signal lines of a local input/output line to an output buffer, comprising:

coupling first and second signal lines of a global input/output line to an internal voltage supply;

decoupling either the first or second signal line of the global input/output line from the internal voltage supply in response to the coupling of the read data to the first and second signal lines of the local input/output line;

developing a voltage differential at first and second nodes in response to a current differential resulting from the decoupling of the first or second signal line from the internal voltage supply, respectively;

driving the voltage of the decoupled signal line of the global input/output line at the respective node to a voltage level greater than the voltage level of the respective node of the signal line of the global input/output line coupled to the internal voltage supply; and

coupling the first and second nodes to an input of the output buffer.

37. The method of claim 36 wherein developing a voltage differential at the first and second node comprises increasing a voltage drop across an active load coupled to the internal voltage supply in response to increasing current.

38. The method of claim 36 wherein driving the voltage of the decoupled signal line of the global input/output line comprises latching the voltage levels at that first and second nodes through cross coupled n-channel MOS transistors.