Register bank

• US 6,944,739 B2
• Filed: 09/20/2001
• Issued: 09/13/2005
• Est. Priority Date: 09/20/2001
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Microchip Technology Incorporated
• Inventors: Bartling, James R., Yach, Randy, Thomsen, Joseph A.
• Primary Examiner(s): NGUYEN, THAN VINH
• Application Number:
  US09/957,283
• Publication Number:
  US 20040151047A1
• Time in Patent Office: 1,454 Days
• Field of Search: 711/1, 711/5, 711/154, 711/168, 710/29, 710/49
• US Class Current: 711/168
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A filter register bank, for example, for a CAN module provides parallel and serial access. The filter bank comprises a plurality of memory cells arranged in a matrix of columns and rows, wherein for parallel access all memory cells within a row are selectable and coupled with a first plurality of bus lines and for serial access all memory cells within a column are selectable and coupled with a second plurality of bus lines.

Claims

1. A filter register bank for a CAN module providing parallel and serial access comprising:

a plurality of memory cells arranged in a matrix of columns and rows, wherein for parallel access all memory cells within a row are selectable and coupled with a first plurality of bus lines and for serial access all memory cells within a column are selectable and coupled with a second plurality of bus lines.

2. The filter register bank according to claim 1, wherein each memory cell comprises a hold element being coupled with a first and second transfer gate for coupling with said first and second bus lines, respectively.

3. The filter register bank according to claim 2, wherein said hold element comprises two inverters coupled in series.

4. The filter register bank according to claim 3, wherein each bus line comprises a non-inverting and an inverting bus line and each memory cell comprises a pair of first transfer gates and a pair of second transfer gates coupled with the input and output of said inverters, respectively.

5. A CAN module receiving a serial bit stream comprising:

a filter register comprising a plurality of memory cells arranged in a matrix of columns and rows, wherein for parallel access all memory cells within a row are selectable and coupled with a first plurality of bus lines and for serial access all memory cells within a column are selectable and coupled with a second plurality of bus lines;

a column select unit for selecting a column of said filter register bank in accordance with said serial bit stream;

a plurality of comparators coupled with said single bit column and with said serial bit stream for generating a plurality of comparison signals; and

a plurality of registers receiving said plurality of comparison signals for accumulating a plurality of comparison results for each comparison and for generating a plurality of acceptance signals.

6. A CAN module according to claim 5, further comprising

a mask register having a bit select input and a single bit output;

a plurality of mask units receiving said mask single bit output and said plurality of comparison results and generating a plurality of result signals being fed to said plurality of registers.

7. A CAN module according to claim 6, further comprising

at least two mask registers having a bit select input and a single bit output;

a plurality of multiplexers for selecting one of said mask register single bit outputs.

8. A CAN module according to claim 7, wherein each multiplexer comprises an input which is coupled with the single bit output of one of said filter register.

9. A CAN module according to claim 7, wherein each multiplexer comprises an input which is coupled with a constant signal indicating no mask function.

10. A CAN module according to claim 7, wherein each multiplexer is controlled by at least one bit from a respective filter register.

11. A CAN module according to claim 10, wherein each filter register comprises two additional bits to control said multiplexer.

12. A CAN module according to claim 5, wherein one of said comparators is an EXCLUSIVE NOR gate.

13. A CAN module according to claim 6, wherein a mask unit is a NOR gate.

14. A CAN module according to claim 5, wherein said register is a D-Flip-Flop.

15. A CAN module according to claim 5, wherein each memory cell comprises a hold element being coupled with a first and second transfer gate for coupling with said first and second bus lines, respectively.

16. A CAN module according to claim 15, wherein said hold element comprises two inverters coupled in series.

17. A CAN module according to claim 5, wherein each bus line comprises a non-inverting and an inverting bus line and each memory cell comprises a pair of first transfer gates and a pair of second transfer gates coupled with the input and output of said inverters, respectively.

18. A method of operating a CAN module comprising the steps of:

writing a filter value in parallel into a filter bank;

receiving a data stream including an identifier and data;

comparing said identifier with a plurality of filter values on a bit by bit basis;

generating an acceptance signal for each comparison if said identifier comparison is positive.

19. A method according to claim 18, further comprising the step of masking said comparison result on a bit by bit basis.

20. A method according to claim 19, further comprising the step of selecting a mask value from a plurality of mask values.

21. A method according to claim 20, wherein said filter value provides additional data information for selecting said mask value.

22. A method according to claim 20, wherein said mask values is selected from a plurality of mask registers and filter registers.

23. A method according to claim 20, wherein one mask value provides a non-masking function.

24. A register bank providing parallel and serial access comprising:

a plurality of memory cells arranged in a matrix of columns and rows, wherein for parallel access all memory cells within a row are selectable and coupled with a first plurality of bus lines and for serial access all memory cells within a column are selectable and coupled with a second plurality of bus lines, wherein each memory cell comprises a hold element being coupled with a first and second transfer sate for coupling with said first and second bus lines, respectively.

25. The register bank according to claim 24, wherein said hold element comprises two inverters coupled in series.

26. The register bank according to claim 25, wherein each bus line comprises a non-inverting and an inverting bus line and each memory cell comprises a pair of first transfer gates and a pair of second transfer gates coupled with the input and output of said inverters, respectively.