Method and apparatus for proportionate costing of vias
First Claim
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1. A method of routing nets in an integrated-circuit layout region, the region having a plurality of interconnect layers, the method comprising:
- (a) specifying a plurality of routes, wherein some of the routes utilize vias to traverse multiple interconnect layers; and
(b) assessing a via cost of at least one via proportionately to a cost that the via introduces in the design of the integrated circuit, wherein a via introduces a cost in the design that is greater than the cost of a particular route length by a particular multiplier, and (c) specifying the via cost according to the particular multiplier.
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Abstract
Some embodiments of the invention provide a method of routing nets in an integrated-circuit layout region that has multiple interconnect layers. The method specifies several routes, where some of the routes utilize vias to traverse multiple interconnect layers. The method assesses a cost of at least one via proportionately to a cost that the via introduces in the design of the integrated circuit.
115 Citations
21 Claims
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1. A method of routing nets in an integrated-circuit layout region, the region having a plurality of interconnect layers, the method comprising:
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(a) specifying a plurality of routes, wherein some of the routes utilize vias to traverse multiple interconnect layers; and
(b) assessing a via cost of at least one via proportionately to a cost that the via introduces in the design of the integrated circuit, wherein a via introduces a cost in the design that is greater than the cost of a particular route length by a particular multiplier, and (c) specifying the via cost according to the particular multiplier. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of routing nets in an integrated-circuit layout region, the region having a plurality of interconnect layers, the method comprising:
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(a) specifying a plurality of routes, wherein some of the routes utilize vias to traverse multiple interconnect layers;
(b) assessing a cost of at least one via proportionately to a cost that the via introduces in the design of the integrated circuit; and
(c) assessing a length cost for each route, wherein the via introduces a resistance in the design that is greater than the resistance of a particular route length by a particular multiplier, wherein assessing the cost of the via comprises specifying the via'"'"'s cost according to the particular multiplier.
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12. A method of routing nets in an integrated-circuit layout region, the region having a plurality of interconnect layers, the method comprising:
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(a) specifying a plurality of routes, wherein some of the routes utilize vias to traverse multiple interconnect layers;
(b) assessing a cost of at least one via proportionately to a cost that the via introduces in the design of the integrated circuit; and
(c) assessing a length cost for each route, wherein the via introduces a delay in the design that is greater than the delay of a particular route length by a particular multiplier, wherein assessing the cost of the via comprises specifying the via'"'"'s cost according to the particular multiplier.
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13. A computer readable medium that stores a computer program having executable code, the computer program for routing nets in an integrated-circuit layout region, the region having a plurality of interconnect layers, the computer program comprising sets of instructions for:
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(a) specifying a plurality of routes, wherein some of the routes utilize vias to traverse multiple interconnect layers; and
(b) assessing a via cost of at least one via proportionately to a cost that the via introduces in the design of the integrated circuit, wherein a via introduces a cost in the design that is greater than the cost of a particular route length by a particular multiplier; and
(c) specifying the via cost according to the particular multiplier. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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20. A computer readable medium that stores a computer program having executable code, the computer program for routing nets in an integrated-circuit layout region, the region having a plurality of interconnect layers, the computer program comprising sets of instructions for:
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(a) specifying a plurality of routes, wherein some of the routes utilize vias to traverse multiple interconnect layers;
(b) assessing a cost of at least one via proportionately to a cost that the via introduces in the design of the integrated circuit; and
(c) assessing a length cost for each route, wherein the via introduces a resistance in the design that is greater than the resistance of a particular route length by a particular multiplier, wherein the set of instructions for assessing the cost of the via comprises a set of instructions for specifying the via'"'"'s cost according to the particular multiplier.
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21. A computer readable medium that stores a computer program having executable code, the computer program for routing nets in an integrated-circuit layout region, the region having a plurality of interconnect layers, the computer program comprising sets of instructions for:
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(a) specifying a plurality of routes, wherein some of the routes utilize vias to traverse multiple interconnect layers;
(b) assessing a cost of at least one via proportionately to a cost that the via introduces in the design of the integrated circuit; and
(c) assessing a length cost for each route, wherein the via introduces a delay in the design that is greater than the delay of a particular route length by a particular multiplier, wherein the set of instructions for assessing the cost of the via comprises a set of instructions for specifying the via'"'"'s cost according to the particular multiplier.
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Specification