Apparatus for evaluating amount of charge, method for fabricating the same, and method for evaluating amount of charge

• US 6,946,305 B2
• Filed: 10/15/2003
• Issued: 09/20/2005
• Est. Priority Date: 12/06/2002
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Sengoku, Naohisa, Matsumoto, Michikazu
• Primary Examiner(s): MENZ, LAURA MARY
• Application Number:
  US10/684,465
• Publication Number:
  US 20040110315A1
• Time in Patent Office: 706 Days
• Field of Search: 438/14, 438/17, 438/18, 438/15, 438/10, 438/11, 438/452, 438/250, 438/393, 438/4, 438/9
• US Class Current: 438/14
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

A wafer for charge amount evaluation having a silicon substrate and p-type regions sandwiched between a first silicon oxide film and a SA-NSG film and surrounded by an undoped silicon film is prepared and subjected to a target process for which an amount of charge is to be evaluated. Then, etching is performed by using a BHF solution. By measuring an amount of etching in the p-type region, an amount of positive charge caused by the process in the wafer can be evaluated quantitatively in an easy and convenient manner.

Claims

1. A method for evaluating an amount of charge, the method comprising the steps of:

(a) preparing an apparatus for evaluating an amount of charge, the apparatus comprising a semiconductor substrate having a first insulating film on an upper portion thereof, a substantially intrinsic undoped silicon layer provided on the first insulating film, p-type regions each surrounded by the undoped silicon layer and composed of silicon containing a p-type impurity , and a second insulating film provided over the undoped silicon layer and the p-type regions;

(b) performing a specified process with respect to the apparatus for evaluating an amount of charge;

(c) after the step (b) immersing the apparatus for evaluating an amount of charge in an etching solution and etching at least the p-type regions in accordance with a principle of anodization; and

(d) calculating, from an amount of etching in each of the p-type regions, an amount of charge caused b the specified process in the apparatus for evaluating an amount of charge.

2. The method of claim 1, wherein the etching solution used in the step (c) contains ions including those of F atoms.

3. The method of claim 1, wherein the step (d) includes calculating the amount of etching in each of the p-type regions from a change in a weight of the p-type region.

4. The method of claim 1, wherein

the apparatus for evaluating an amount of charge further comprises a back-surface insulating film provided on a back surface of the semiconductor substrate and

the specified process in the step (b) is a back-surface scrubbing process for cleaning the back-surface insulating film.

5. The method of claim 1, wherein the specified process in the step (b) is ion implantation.

6. The method of claim 1, wherein

the apparatus for evaluating an amount of charge further comprises a conductor film provided on the second insulating film and

the specified process the step (b) is dry etching of the conductor film.