Method of manufacturing a semiconductor device and a fabrication apparatus for a semiconductor device

• US 6,946,306 B2
• Filed: 11/09/2004
• Issued: 09/20/2005
• Est. Priority Date: 02/15/2000
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi Tohbu Semiconductor, Ltd. (Renesas Electronics Corporation), Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Kobayashi, Yoshihiko, Ishizu, Akio, Takada, Susumu, Ida, Tsutomu, Takashima, Kazutoshi, Haga, Shigeru, Oba, Shiro, Koujiro, Iwamichi, Kakegawa, Yuji, Arai, Norinaga
• Primary Examiner(s): Thompson, Craig A.
• Assistant Examiner(s): Harrison, Monica D.
• Application Number:
  US10/983,689
• Publication Number:
  US 20050064612A1
• Time in Patent Office: 315 Days
• Field of Search: 438/691, 438/106, 438/72, 438/31, 438/29, 438/15, 435/287.1, 435/6, 422/68.1
• US Class Current: 438/15
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2223/54406 comprising alphanumeric information
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2223/54486 Located on package parts, e.g. encapsulation, leads, package substrate
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/04 characterised by the shape of the container or parts, e.g. caps, walls
• CPC Class Codes: H01L 23/10 : characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/13 : characterised by the shape
• CPC Class Codes: H01L 23/49805 : the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 23/50 : for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/165 : Containers
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15313 : being a land array, e.g. LGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/16315 : Shape
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate

Abstract

A method of manufacturing a semiconductor device able to reduce the number of manufacturing steps and attain the rationalization of a manufacturing line is disclosed. The semiconductor device is a high-frequency module assembled by mounting chip parts (22) and semiconductor pellets (21) onto each of wiring substrates (2) formed on a matrix substrate (27) after inspection. A defect mark (2e) is affixed to a wiring substrate (2) as a block judged to be defective in the inspection of the matrix substrate (27), then in a series of subsequent assembling steps the defect mark (e) is recognized and the assembling work for the wiring substrate (2) with the defect mark (2e) thereon is omitted to attain the rationalization of a manufacturing line.

Claims

1. A method of manufacturing a semiconductor device which is assembled by dividing a matrix substrate along dividing grooves, the matrix substrate having wiring patterns formed on a second main surface thereof in a manner spanning the dividing grooves, the second main surface being located on the side opposite to a first main surface of the matrix substrate on which the dividing grooves to partition plural wiring substrates of the matrix substrate are formed, the method comprising the steps of:

(a) causing a dividing portion contiguous to a remaining portion of the matrix substrate to project and supporting the remaining portion by the second main surface thereof, with plural caps being attached to the first main surface of the matrix substrate correspondingly to the wiring substrates; and

(b) causing the dividing portion of the matrix substrate to pivot to the second main surface side to divide the remaining portion and the dividing portion from each other and tearing off the wiring pattern concerned along the associated dividing groove.

2. A method of manufacturing a semiconductor device which is assembled by dividing a matrix substrate along dividing grooves, the matrix substrate having wiring patterns formed on a second main surface thereof in a manner spanning the dividing grooves, the second main surface being located on the side opposite to a first main surface of the matrix substrate on which the dividing grooves to partition plural wiring substrates of the matrix substrate are formed, the method comprising the steps of:

(a) causing a dividing portion contiguous to a remaining portion of the matrix substrate to project and supporting the remaining portion by the second main surface thereof; and

(b) displacing a pivot center in both a direction perpendicular to the second main surface from a dividing position where any of the dividing grooves is formed and a direction of the dividing portion from the dividing position, the pivot center being a center of pivoting the dividing portion of the matrix substrate to the second main surface side, allowing the dividing portion to pivot in this state to divide the remaining portion and the dividing portion from each other, and tearing off the wiring pattern concerned along the associated dividing groove.

3. A method of manufacturing a semiconductor device which is assembled by dividing a matrix substrate along dividing grooves, the matrix substrate having wiring patterns formed on a second main surface thereof in a manner spanning the dividing grooves, the second main surface being located on the side opposite to a first main surface of the matrix substrate on which the dividing grooves to partition plural wiring substrates of the matrix substrate are formed, the method comprising the steps of:

(a) causing a dividing portion contiguous to a remaining portion of the matrix substrate to project and supporting the remaining portion by the second main surface thereof; and

(b) dividing the matrix substrate into the remaining portion and the dividing portion and thereafter tearing off the wiring pattern concerned along the associated dividing groove.

4. A method of manufacturing a semiconductor device which is assembled by dividing a matrix substrate along dividing grooves, the matrix substrate having wiring patterns formed on a second main surface thereof in a manner spanning the dividing grooves, the second main surface being located on the side opposite to a first main surface of the matrix substrate on which the dividing grooves to partition plural wiring substrates of the matrix substrate are formed, the method comprising the steps of:

(a) causing a dividing portion contiguous to a remaining portion of the matrix substrate to project and supporting the remaining portion by the second main surface thereof; and

(b) when dividing the matrix substrate into the remaining portion and the dividing portion along any of the dividing groove, beginning the dividing work with one end of the dividing groove.

5. A method of manufacturing a semiconductor device which is assembled by dividing a matrix substrate along dividing grooves, the matrix substrate having wiring patterns formed on a second main surface thereof in a manner spanning the dividing grooves, the second main surface being located on the side opposite to a first main surface of the matrix substrate on which the dividing grooves to partition plural wiring substrates of the matrix substrate are formed, the method comprising the steps of:

(a) causing a dividing portion contiguous to the remaining portion of the matrix substrate to project and supporting the remaining portion by the second main surface thereof, with plural caps being attached to the first main surface of the matrix substrate correspondingly to the wiring substrates; and

(b) displacing a pivot center in both a direction perpendicular to the second main surface from a dividing position where any of the dividing grooves is formed and a direction of the dividing portion from the dividing position, the pivot center being a center of pivoting the dividing portion of the matrix substrate to the second main surface side, allowing the dividing portion to pivot in this state to divide the remaining portion and the dividing portion from each other, and tearing off the wiring pattern concerned along the associated dividing groove.

6. A method of manufacturing a semiconductor device which is assembled by dividing a matrix substrate along dividing grooves, the matrix substrate having wiring patterns formed on a second main surface thereof in a manner spanning the dividing grooves, the second main surface being located on the side opposite to a first main surface of the matrix substrate on which the dividing grooves to partition plural wiring substrates of the matrix substrate are formed, the method comprising the steps of:

(a) causing a dividing portion contiguous to a remaining portion of the matrix substrate to project and supporting the remaining portion by the second main surface thereof, with plural caps being attached to the first main surface of the matrix substrate correspondingly to the wiring substrates; and

(b) pivoting the dividing portion of the matrix substrate to the second main surface side to divide the remaining portion and the dividing portion from each other and thereafter tearing off the wiring pattern concerned along the associated dividing groove.

7. A method of manufacturing a semiconductor device which is assembled by dividing a matrix substrate along dividing grooves, the matrix substrate having wiring patterns formed on a second main surface thereof in a manner spanning the dividing grooves, the second main surface being located on the side opposite to a first main surface of the matrix substrate on which the dividing grooves to partition plural wiring substrates of the matrix substrate are formed, the method comprising the steps of:

(a) causing a dividing portion contiguous to a remaining portion of the matrix substrate to project and supporting the remaining portion by the second main surface thereof, with plural caps being attached to the first main surface of the matrix substrate correspondingly to the wiring substrates; and

(b) when pivoting the dividing portion of the matrix substrate to the second main surface side to divide the remaining portion and the dividing portion from each other along any of the dividing grooves, beginning the dividing work with one end of the dividing groove and tearing off the wiring pattern concerned along the associated dividing groove.

8. A method of manufacturing a semiconductor device which is assembled by dividing a matrix substrate along dividing grooves, the matrix substrate having wiring patterns formed on a second main surface thereof in a manner spanning the dividing grooves, the second main surface being located on the side opposite to a first main surface of the matrix substrate on which the dividing grooves to partition plural wiring substrates of the matrix substrate are formed, the method comprising the steps of:

(a) causing a dividing portion contiguous to a remaining portion of the matrix substrate to project and supporting the remaining portion by the second main surface thereof, with plural caps being attached to the first main surface of the matrix substrate correspondingly to the wiring substrates; and

(b) displacing a pivot center in both a direction perpendicular to the second main surface from a dividing position where any of the dividing grooves is formed and a direction of the dividing portion from the dividing position, the pivot center being a center of pivoting the dividing portion of the matrix substrate to the second main surface side, allowing the dividing portion to pivot in this state to divide the remaining portion and the dividing portion from each other, beginning with one end of the dividing groove, and tearing off the wiring pattern concerned along the dividing groove.

9. A method of manufacturing a semiconductor device which is assembled by dividing a matrix substrate along dividing grooves, the matrix substrate having wiring patterns formed on a second main surface thereof in a manner spanning the dividing grooves, the second main surface being located on the side opposite to a first main surface of the matrix substrate on which the dividing grooves to partition the plural wiring substrates of the matrix substrate are formed, the method comprising the steps of:

(a) disposing the matrix substrate onto a dividing support base in a substrate dividing apparatus;

(b) causing a dividing portion contiguous to a remaining portion of the matrix substrate to project and supporting the second main surface of the remaining portion by the dividing support base, with plural caps being attached to the first main surface correspondingly to the wiring substrates; and

(c) pivoting the dividing portion of the matrix substrate to the second main surface side, applying a load to the first main surface of the dividing portion by a loading portion which is provided interlockably with a movable portion of the dividing support base correspondingly to the first main surface of the dividing portion to divide the matrix substrate into the remaining portion and the dividing portion, and tearing off the wiring pattern concerned along the associated dividing groove.

10. A method of manufacturing a semiconductor device which is assembled by dividing a matrix substrate along dividing grooves, the matrix substrate having wiring patterns formed on a second main surface thereof in a manner spanning the dividing grooves, the second main surface being located on the side opposite to a first main surface of the matrix substrate on which the dividing grooves to partition plural wiring substrates of the matrix substrate are formed, the method comprising the steps of:

(a) disposing the matrix substrate onto a dividing support base in a substrate dividing apparatus;

(b) causing a dividing portion contiguous to a remaining portion of the matrix substrate to project and supporting the second main surface of the remaining portion by the dividing support base; and

c) pivoting the dividing portion of the matrix substrate to the second main surface side, applying a load to one end of the first main surface of the dividing portion by a loading portion which is provided interlockably with a movable portion of the dividing support base correspondingly to the first main surface of the dividing portion to divide the matrix substrate. into the remaining portion and the dividing portion, beginning with one end of the associated dividing groove, and tearing off the wiring pattern concerned along the dividing groove.

11. A method of manufacturing a semiconductor device which is assembled by dividing a matrix substrate along dividing grooves, the matrix substrate having wiring patterns formed on a second main surface thereof in a manner spanning the dividing grooves, the second main surface being located on the side opposite to a first main surface of the matrix substrate on which the dividing grooves to partition plural wiring substrates of the matrix substrate are formed, the method comprising the steps of:

(a) mounting a surface-mounted type electronic part and a bare chip-mountable semiconductor pellet onto each of the wiring substrates;

(b) attaching a plurality of caps to the first main surface of the matrix substrate correspondingly to the wiring substrates;

(c) causing a dividing portion contiguous to a remaining portion of the matrix substrate with the plural caps attached to the first main surface to project and supporting the remaining portion by the second main surface thereof; and

(d) pivoting the dividing portion of the matrix substrate to the second main surface side to divide the matrix substrate into the remaining portion and the dividing portion and tearing off the wiring pattern concerned along the associated dividing groove.

12. A method of manufacturing a semiconductor device which is assembled by dividing a matrix substrate along dividing grooves, the matrix substrate having wiring patterns formed on a second main surface thereof in a manner spanning the dividing grooves, the second main surface being located on the side opposite to a first main surface of the matrix substrate on which the dividing grooves to partition plural wiring substrates of the matrix substrate are formed, the method comprising the steps of:

causing a dividing portion contiguous to a remaining portion of the matrix substrate to project and supporting the remaining portion by the second main surface thereof; and

(b) displacing a pivot center in both a direction perpendicular to the second main surface from a dividing position where any of the dividing grooves is formed and a direction of the dividing portion from the dividing position, the pivot center being a center of pivoting the dividing portion of the matrix substrate to the second main surface side, allowing the dividing portion to pivot in this state to divide the remaining portion and the dividing portion from each other, and thereafter tearing off the wiring pattern concerned along the associated dividing groove.

13. A method of manufacturing a semiconductor device which is assembled by dividing a matrix substrate along dividing grooves, the matrix substrate having wiring patterns formed on a second main surface thereof in a manner spanning the dividing grooves, the second main surface being located on the side opposite to a first main surface of the matrix substrate on which the dividing grooves to partition plural wiring substrates of the matrix substrate are formed, the method comprising the steps of:

(a) causing a dividing portion contiguous to a remaining portion of the matrix substrate to project and supporting the remaining portion by the second main surface thereof; and

(b) displacing a pivot center in both a direction perpendicular to the second main surface from a dividing position where any of the dividing grooves is formed and a direction of the dividing portion from the dividing position, the pivot center being a center of pivoting the dividing portion of the matrix substrate to the second main surface side, allowing the dividing portion to pivot in this state to divide the remaining portion and the dividing portion from each other, beginning with one end of the associated dividing groove, and tearing off the wiring pattern concerned along the dividing groove.

14. A method of manufacturing a semiconductor device, comprising the steps of:

(a) supporting a matrix substrate with plural caps mounted on a first main surface thereof correspondingly to wiring substrates, the wiring substrates being formed on the matrix substrate and each having a semiconductor pellet mounted thereon; and

(b) bending the matrix substrate automatically to the side opposite to the first main surface and tearing of f a wiring pattern concerned out of wiring patterns formed on a second main surface of the matrix substrate located on the side opposite to the first main surface.

15. A method of manufacturing a semiconductor device, comprising the steps of:

(a) supporting a matrix substrate with plural caps mounted on a first main surface thereof correspondingly to wiring substrates, the wiring substrates being formed on the matrix substrate and each having an integrated circuit pellet mounted thereon;

(b) bending and dividing the matrix substrate automatically while displacing a center of the division from a dividing point, the matrix substrate having wiring patterns formed on a surface thereof located on the side smaller than 180 degrees in terms of a surface-to-surface angle, the wiring patterns spanning dividing grooves, and tearing off the wiring pattern concerned.

16. The method of claim 15, wherein the matrix substrate is divided along the dividing grooves while displacing the center of the division in both a direction perpendicular to the second main surface opposite to the first main surface from the dividing point and an outward direction from the dividing point.

17. A method of manufacturing a semiconductor device, comprising the steps of:

(a) supporting a matrix substrate with plural caps mounted on a first main surface thereof correspondingly to wiring substrates, the wiring substrates each having an integrated circuit pellet mounted thereon; and

(b) bending and dividing the matrix substrate automatically in accordance with a process comprising the following steps, the matrix substrate having wiring patterns formed on its bent side so as to span dividing grooves;

(i) dividing the matrix substrate; and

(ii) tearing off the wiring patterns.

18. A method of manufacturing a semiconductor device, comprising the steps of:

(a) supporting a matrix substrate with plural caps mounted on a first main surface thereof correspondingly to wiring substrates, the wiring substrates each having an integrated circuit pellet mounted thereon; and

(b) bending and dividing the matrix substrate automatically with use of a dividing tool and in accordance with a process comprising the following steps, the matrix substrate having wiring patterns formed on its bent side so as to span dividing grooves;

(i) forming a crack in one end of each of the dividing grooves of the matrix substrate; and

(ii) allowing the crack to be propagated to an opposite end of the dividing groove.