Method for microfabricating structures using silicon-on-insulator material

• US 6,946,314 B2
• Filed: 08/15/2003
• Issued: 09/20/2005
• Est. Priority Date: 01/02/2001
• Status: Active Grant

• Current Assignee: Charles Stark Draper Laboratory Incorporated
• Original Assignee: Charles Stark Draper Laboratory Incorporated
• Inventors: Borenstein, Jeffrey T., Sawyer, William D.
• Primary Examiner(s): Blum, David S.
• Application Number:
  US10/642,315
• Publication Number:
  US 20040102021A1
• Time in Patent Office: 767 Days
• Field of Search: 438/48, 438/50, 438/456
• US Class Current: 438/50
• CPC Class Codes: B81C 1/00182 Arrangements of deformable or non-deformable structures, e.g. membrane and cavity for use in a transducer
• CPC Class Codes: B81C 1/00579 Avoid charge built-up
• CPC Class Codes: B81C 2201/0191 Transfer of a layer from a carrier wafer to a device wafer
• CPC Class Codes: B81C 3/001 Bonding of two components

Abstract

The invention provides a general fabrication method for producing MicroElectroMechanical Systems (MEMS) and related devices using Silicon-On-Insulator (SOI) wafer. The method includes providing an SOI wafer that has (i) a handle layer, (ii) a dielectric layer, and (iii) a device layer, wherein a mesa etch has been made on the device layer of the SOI wafer, providing a substrate, wherein a pattern has been etched onto the substrate, bonding the SOI wafer and the substrate together, removing the handle layer of the SOI wafer, removing the dielectric layer of the SOI wafer, then performing a structural etch on the device layer of the SOI wafer to define the device.

Claims

1. A method for producing micromachined devices, comprising the steps of:

(a) obtaining a Silicon-On-Insulator (SOI) wafer, which comprises

(i) a handle layer,

(ii) a dielectric layer, and

(iii) a device layer;

wherein a mesa etch has been made on the device layer of the SOI wafer,

(b) obtaining a substrate, wherein a pattern has been formed onto the substrate;

(c) bonding the SOI wafer and the substrate together;

(d) removing the handle layer of the SOI wafer;

(e) removing the dielectric layer of the SOI wafer; and

(f) after step (e), performing a structural etch on the device layer.

2. The method of claim 1, wherein the dielectric layer of the SOI wafer comprises silicon dioxide.

3. The method of claim 1, wherein the structural etch is a Deep Reactive Ion Etch.

4. The method of claim 1, wherein the substrate comprises at least one access port.

5. The method of claim 1, wherein the substrate is glass or silicon.

6. The method of claim 1, wherein the substrate is glass and the substrate pattern comprises multilevel metallization.

7. The method of claim 1, wherein the substrate is a recess-etched glass wafer.

8. The method of claim 7, further comprising the steps of

(a) performing a blanket sputter of the multilevel metallization;

and

(b) lifting off the metal not directly applied to the substrate.

9. The method of claim 1, wherein the bonding of the SOI wafer and the substrate is anodic bonding.

10. The method of claim 1, wherein removing the handle layer of the SOI wafer comprises removing the handle layer of the SOI wafer by a wet chemical etch.

11. The method of claim 1, wherein removing the dielectric layer of the SOI wafer comprises removing the dielectric layer of the SOI wafer by a dry plasma etch.

12. The method of claim 1, wherein said substrate comprises an SOI wafer.

13. The method of claim 1, wherein the structural etch is straight down through the device layer to the substrate.

14. The method of claim 13, wherein the device layer is partially removed at the top surface at locus where the structural etch is to be performed straight down to the substrate, such that when the device layer is bonded to the substrate, the surface of the device layer at the locus is spaced apart from the substrate.

15. The method of claim 1, wherein said substrate includes a patterned metal layer deposited thereon, wherein the metal layer defines gaps, which are positioned other than under operable elements which is to be formed by etching the device layer.

16. The method of claim 1, wherein bonding the SOI wafer and the substrate together is performed under a predetermined pressure less than atmosphere pressure.

17. The method of claim 1, wherein removing the handle layer of the SOI wafer comprises:

(a). removing the handle layer of the SOI wafer to a predetermined distance from the dielectric layer by a first etchant, wherein a relatively thin handle layer is left on the dielectric layer; and

(b). removing the relatively thin handle layer by a second etchant.

18. The method of claim 17, wherein said first etchant is a relatively fast etchant.

19. The method of claim 17, wherein said second etchant is a relatively slow etchant.

20. The method of claim 17, wherein said first etchant is potassium hydroxide (XeF₂).

21. The method of claim 17, wherein said second etchant is xenon difluoride (XeF₂).

22. The method of claim 17, wherein said second etchant is tetramethyl ammonium hydroxide (TMAH).

23. A method for making an accelerometer, comprising the steps of:

(a) obtaining a Silicon-On-Insulator (SOI) wafer, which comprises

(i) a handle layer,

(ii) a dielectric layer, and

(iii) a device layer;

wherein a mesa etch has been made on the device layer of the SOI wafer;

(b) obtaining a substrate, wherein a pattern has been formed onto the substrate;

(c) bonding the SOI wafer and the substrate together;

(d) removing the handle layer of the SOI wafer;

(e) removing the dielectric layer of the SOI wafer; and

(f) after step (e), performing a structural etch on the device layer, such that the etches of the mesa etch and the structural etch provide a pattern for an accelerometer.