Method of forming the integrated circuit having a die with high Q inductors and capacitors attached to a die with a circuit as a flip chip

• US 6,946,321 B1
• Filed: 05/26/2004
• Issued: 09/20/2005
• Est. Priority Date: 12/05/2001
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Yegnashankaran, Visvamohan, Padmanabhan, Gobi R.
• Primary Examiner(s): Smoot, Stephen W.
• Application Number:
  US10/853,875
• Time in Patent Office: 482 Days
• Field of Search: 438/107, 438/108, 438/110, 438/612, 438/613, 438/617
• US Class Current: 438/107
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 27/292 Surface mounted devices
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/49112 the connectors connecting a common bonding area on the semiconductor or solid-state body to different bonding areas outside the body, e.g. diverging wires
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/49179 Corner adaptations, i.e. disposition of the wire connectors at the corners of the semiconductor or solid-state body
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A semiconductor integrated circuit with high Q inductors and capacitors is disclosed. A semiconductor electrical circuit is formed on a first die, while micro-electromechanical structures having inductance and capacitance are formed on a second die. The second die is attached and electrically connected to the first die as a flip chip.

Claims

1. A method of forming an integrated circuit, the method comprising the steps of:

forming a first die from a first wafer, the first die having;

a substrate with an electrical circuit;

an interconnect formed on the substrate and electrically connected to the electrical circuit;

a passivation layer formed on the interconnect;

a plurality of first bonding pads formed on the passivation layer, the first bonding pads being electrically connected to the interconnect; and

a plurality of second bonding pads formed on the passivation layer, the second bonding pads being electrically connected to the interconnect;

forming a second die from a second wafer, the second die having;

a micro-electromechanical structure having an inductance; and

a plurality of third bonding pads, the micro-electromechanical structure being connected to a third bonding pad; and

attaching the third bonding pads of the second die to the second bonding pads of the first die.

2. The method of claim 1 wherein the first die is fabricated at a first facility using a first sequence of fabrication steps and the second die is fabricated at a second facility using a different second sequence of fabrication steps.

3. The method of claim 2 wherein the third bonding pads of the second die are attached to the second bonding pads of the first die at the first facility.

4. The method of claim 2 wherein the third bonding pads of the second die are attached to the second bonding pads of the first die at the second facility.

5. The method of claim 1 wherein the first die is fabricated at a facility using a first sequence of fabrication steps and the second die is fabricated at the facility using a different second sequence of fabrication steps.

6. The method of claim 1 wherein the third bonding pads of the second die are attached to the second bonding pads of the first die at a third facility.

7. The method of claim 1 and further comprising the step of attaching the first die to a semiconductor package, the semiconductor package having a plurality of fourth bonding pads, a plurality of circuit board connectors, and internal routing that electrically connects the plurality of fourth bonding pads to the plurality of circuit board connectors.

8. The method of claim 7 wherein the first die is fabricated at a first facility using a first sequence of fabrication steps, the second die is fabricated at a second facility using a different second sequence of fabrication steps, the third bonding pads of the second die are attached to the second bonding pads of the first die at a third facility, and the first die is attached to the semiconductor package at the third facility.

9. The method of claim 7 wherein the first die is fabricated at a first facility using a first sequence of fabrication steps, the second die is fabricated at a second facility using a different second sequence of fabrication steps, the third bonding pads of the second die are attached to the second bonding pads of the first die at a third facility, and the first die is attached to the semiconductor package at a fourth facility.

10. The method of claim 7 wherein the first die is fabricated at a first facility using a first sequence of fabrication steps, the second die is fabricated at a second facility using a different second sequence of fabrication steps, the third bonding pads of the second die are attached to the second bonding pads of the first die at the first facility, and the first die is attached to the semiconductor package at the first facility.

11. The method of claim 7 wherein the first die is fabricated at a first facility using a first sequence of fabrication steps, the second die is fabricated at a second facility using a different second sequence of fabrication steps, the third bonding pads of the second die are attached to the second bonding pads of the first die at the second facility, and the first die is attached to the semiconductor package at the second facility.

12. The method of claim 7 wherein the first die is fabricated at a facility using a first sequence of fabrication steps, the second die is fabricated at the facility using a different second sequence of fabrication steps, the third bonding pads of the second die are attached to the second bonding pads of the first die at the facility, and the first die is attached to the semiconductor package at the facility.

13. The method of claim 7 wherein the first die is fabricated at a first facility using a first sequence of fabrication steps, the second die is fabricated at the first facility using a different second sequence of fabrication steps, the third bonding pads of the second die are attached to the second bonding pads of the first die at a second facility, and the first die is attached to the semiconductor package at the second facility.

14. The method of claim 7 wherein the first die is fabricated at a first facility using a first sequence of fabrication steps, the second die is fabricated at the first facility using a different second sequence of fabrication steps, the third bonding pads of the second die are attached to the second bonding pads of the first die at a second facility, and the first die is attached to the semiconductor package at a third facility.

15. The method of claim 7 and further comprising the step of attaching a plurality of conductive wires to the plurality of first bonding pads and the plurality of fourth bonding pads.

16. The method of claim 15 wherein the first die is fabricated at a first facility using a first sequence of fabrication steps, the second die is fabricated at a second facility using a different second sequence of fabrication steps, the third bonding pads of the second die are attached to the second bonding pads of the first die at a third facility, the first die is attached to the semiconductor package at a fourth facility, and the plurality of conductive wires are attached in the fourth facility.

17. The method of claim 1 wherein the second die further includes a micro-electromechanical structure that has a capacitance, the micro-electromechanical structure having the capacitance being connected to a third bonding pad.