Low voltage high density trench-gated power device with uniformity doped channel and its edge termination technique

• US 6,946,348 B2
• Filed: 03/05/2004
• Issued: 09/20/2005
• Est. Priority Date: 05/03/2002
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Zeng, Jun
• Primary Examiner(s): Coleman, W. David
• Application Number:
  US10/795,723
• Publication Number:
  US 20040171198A1
• Time in Patent Office: 564 Days
• Field of Search: 438/270, 438/424
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Merging together the drift regions in a low-power trench MOSFET device via a dopant implant through the bottom of the trench permits use of a very small cell pitch, resulting in a very high channel density and a uniformly doped channel and a consequent significant reduction in the channel resistance. By properly choosing the implant dose and the annealing parameters of the drift region, the channel length of the device can be closely controlled, and the channel doping may be made highly uniform. In comparison with a conventional device, the threshold voltage is reduced, the channel resistance is lowered, and the drift region on-resistance is also lowered. Implementing the merged drift regions requires incorporation of a new edge termination design, so that the PN junction formed by the P epi-layer and the N⁺ substrate can be terminated at the edge of the die.

Claims

1. A method for manufacturing a power mosfet comprising the steps of:

forming a gate trench mask with open and closed regions on the surface of a semiconductor substrate;

removing semiconductor material from areas exposed by the open regions of the trench mask to form a plurality of gate trenches;

forming a sacrificial gate oxide layer on the sidewalls of the trenches;

implanting the substrate with a drift region implant that penetrates the oxide on the floors of the trenches and is stopped on the surface of the substrate by the residual trench mask;

annealing the substrate to diffuse the drift implant to form a continuous drift layer and define the length of the gate;

removing the trench mask and the sacrificial oxide and forming a gate oxide on the surface of the trench;

depositing a layer of polysilicon on the surface of the substrate and in the trenches;

removing the polysilicon from the surface of the semiconductor substrate and leaving enough polysilicon in the gate trenches to form gates in the trenches;

implanting the substrate with a source dopant to form source regions in the surface of the semiconductor substrate and to increase the conductivity of the polysilicon in the trenches to form gate regions in the trenches;

depositing a layer of BPSG on the substrate;

removing at least apart of the BPSG layer to expose portions of the surface having the source implant;

depositing and patterning a conductive layer over the surface of the substrate to form electrical contacts to the source regions.

2. The method of claim 1 further comprising the steps of:

etching a step having a vertical face and a horizontal ledge on the edge of the die while etching the trenches;

forming a gate runner on an upper surface proximate the vertical face;

forming a heavily doped channel stop region in the horizontal ledge at the edged of the die with dopants of the same polarity as the source region; and

forming a metal contact layer over and in contact with the channel stop region.