SONOS memory device having side gate stacks and method of manufacturing the same

• US 6,946,703 B2
• Filed: 01/09/2004
• Issued: 09/20/2005
• Est. Priority Date: 01/09/2003
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Jo-won, Kim, Chung-woo, Yoon, Se-wook, Ryu, Won-il
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Tran, Mai-Huong
• Application Number:
  US10/753,772
• Publication Number:
  US 20040207002A1
• Time in Patent Office: 620 Days
• Field of Search: 257/324, 257/327, 257/412, 257/E29.309, 257/E29.322
• US Class Current: 257/315
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation

Abstract

In a silicon-oxide-nitride-oxide-silicon (SONOS) memory device and a method of manufacturing the same, a SONOS memory device includes a semiconductor substrate, an insulating layer deposited on the semiconductor substrate, an active layer formed on a predetermined region of the insulating layer and divided into a source region, a drain region, and a channel region, a first side gate stack formed at a first side of the channel region, and a second side gate stack formed at a second side of the channel region opposite the first side of the channel region. In the SONOS memory device, at least two bits of data may be stored in each SONOS memory device, thereby allowing the integration density of the semiconductor memory device to be increased without increasing an area thereof.

Claims

1. A silicon-oxide-nitride-oxide-silicon (SONOS) memory device, comprising:

a semiconductor substrate;

an insulating layer formed on the semiconductor substrate;

an active layer formed on a predetermined region of the insulating layer and divided into a source region, a drain region, and a channel region;

a first side gate stack formed at a first side of the channel region; and

a second side gate stack formed at a second side of the channel region opposite the first side of the channel region.

2. The SONOS memory device as claimed in claim 1, wherein the active layer is a semiconductor silicon layer.

3. The SONOS memory device as claimed in claim 1, wherein the active layer has a carbon nano tube structure.

4. The SONOS memory device as claimed in claim 1, wherein the first and second side gate stacks are formed symmetrically with respect to each other.

5. The SONOS memory device as claimed in claim 1, wherein the first and second side gate stacks are formed asymmetrically with respect to each other.

6. The SONOS memory device as claimed in claim 4, wherein the first side gate stack includes a first memory node and a first side gate conductive layer that are sequentially stacked at the first side of the channel region, and the second side gate stack includes a second memory node and a second side gate conductive layer that are sequentially stacked at the second side of the channel region.

7. The SONOS memory device as claimed in claim 6, wherein the first and second memory nodes are extended over a top surface of the channel region and are connected to each other.

8. The SONOS memory device as claimed in claim 6, wherein the first memory node includes a first tunneling oxide layer, a first trapping layer, and a first blocking oxide layer that are sequentially stacked at the first side of the channel region, and the second memory node includes a second tunneling oxide layer, a second trapping layer, and a second blocking oxide layer that are sequentially stacked at the second side of the channel region.

9. The SONOS memory device as claimed in claim 7, wherein the first memory node includes a first tunneling oxide layer, a first trapping layer, and a first blocking oxide layer that are sequentially stacked at the first side of the channel region, and the second memory node includes a second tunneling oxide layer, a second trapping layer, and a second blocking oxide layer that are sequentially stacked at the second side of the channel region.

10. The SONOS memory device as claimed in claim 8, wherein thicknesses of the first and second tunneling oxide layers are equal to each other.

11. The SONOS memory device as claimed in claim 10, wherein thicknesses of the first and second blocking oxide layers are equal to each other.

12. The SONOS memory device as claimed in claim 11, wherein the thicknesses of the first and second blocking oxide layers are respectively greater than thicknesses of the first and second tunneling oxide layers.

13. The SONOS memory device as claimed in claim 5, wherein the first side gate stack includes a first memory node and a first side gate conductive layer that are sequentially stacked at the first side of the channel region, and the second side gate stack includes a second memory node and a second side gate conductive layer that are sequentially stacked at the second side of the channel region.

14. The SONOS memory device as claimed in claim 13, wherein the first and second memory nodes are extended over a top surface of the channel region and are connected to each other.

15. The SONOS memory device as claimed in claim 13, wherein the first memory node includes a first tunneling oxide layer, a first trapping layer, and a first blocking oxide layer that are sequentially stacked at the first side of the channel region, and the second memory node includes a second tunneling oxide layer, a second trapping layer, and a second blocking oxide layer that are sequentially stacked at the second side of the channel region.

16. The SONOS memory device as claimed in claim 14, wherein the first memory node includes a first tunneling oxide layer, a first trapping layer, and a first blocking oxide layer that are sequentially stacked at the first side of the channel region, and the second memory node includes a second tunneling oxide layer, a second trapping layer, and a second blocking oxide layer that are sequentially stacked at the second side of the channel region.

17. The SONOS memory device as claimed in claim 15, wherein a thickness of the first tunneling oxide layer is equal to a thickness of the first blocking oxide layer.

18. The SONOS memory device as claimed in claim 17, wherein a thickness of the second tunneling oxide layer is equal to a thickness of the second blocking oxide layer.

19. The SONOS memory device as claimed in claim 18, wherein the thicknesses of the second tunneling oxide layer and the second blocking oxide layer are respectively greater than the thicknesses of the first tunneling oxide layer and the first blocking oxide layer.

20. The SONOS memory device as claimed in claim 17, wherein the thickness of the first tunneling oxide layer is equal to a thickness of the second tunneling oxide layer, and a thickness of the second blocking oxide layer is greater than the thickness of the first blocking oxide layer.

21. The SONOS memory device as claimed in claim 17, wherein a thickness of the first trapping layer is smaller than a thickness of the second trapping layer.

22. The SONOS memory device as claimed in claim 21, wherein at least one of a thickness of the second tunneling oxide layer and a thickness of the second blocking oxide layer is greater than the thickness of the first tunneling oxide layer.

23. The SONOS memory device as claimed in claim 17, wherein a thickness of the first trapping layer is equal to a thickness of the second trapping layer, and a thickness of at least one of the second tunneling oxide layer and the second blocking oxide layer is greater than the thickness of the first tunneling oxide layer.

24. The SONOS memory device as claimed in claim 14, wherein a gate conductive layer is formed on the first and second memory nodes that are extended over the top surface of the channel region and connected to each other.