Circuit for measuring on-chip power supply integrity

• US 6,946,846 B2
• Filed: 08/05/2004
• Issued: 09/20/2005
• Est. Priority Date: 03/14/2001
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Corr, William E.
• Primary Examiner(s): DEB, ANJAN K
• Application Number:
  US10/911,575
• Publication Number:
  US 20050007126A1
• Time in Patent Office: 411 Days
• Field of Search: 324/522, 324/678, 324426-428, 324/763, 324/765, 324/658, 324/771, 324/537, 713/300, 716/4, 716/5
• US Class Current: 324/537
• CPC Class Codes: G01R 19/16552 in I.C. power supplies
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: H04L 1/22 using redundant apparatus to increase reliability

Abstract

A test circuit and method for measuring power supply integrity is provided. The circuit may be incorporated on-chip and is small enough to be integrated many times across the surface of the die for measuring integrity parameters at several locations on the chip. The circuit instantaneously measures, e.g., the rail voltage of a power supply, which may be fluctuating at the time of measurement. In addition, the circuit isolates itself from all chip power rails for the duration of the measurement, thereby eliminating any influence of external noise on the measurement. A storage capacitor is charged up to full power rail voltage for powering up a comparator. Then, the comparator is isolated from the power rails and the measurements are taken. Based upon the measurements, certain power supply integrity parameters are quantified including ground bounce and power droop.

Claims

1. A computer readable storage medium storing a computer readable program for measuring a parameter of a circuit under test, said computer readable program being configured to operate a computer to:

(a) charge a first portion of a test circuit up to a first voltage level;

(b) charge a second portion of said test circuit up to a second voltage level;

(c) disconnect said test circuit from respective voltage terminals providing said first and second voltage levels; and

(d) measure said parameter of said circuit under test with said test circuit.

2. The storage medium of claim 1, wherein said program is further configured to operate said computer to charge a first capacitor of said test circuit to a power rail voltage level, and also to charge a second portion comprises charging a second capacitor of said test circuit to a predetermined reference voltage level.

3. The storage medium of claim 2, wherein said program is further configured to operate said computer to charge said first capacitor to Vdd.

4. The storage medium of claim 2, wherein said program is further configured to operate said computer to charge said second capacitor to an initial reference voltage level.

5. The storage medium of claim 2, wherein said program is further configured to operate said computer to:

change said predetermined reference voltage level; and

repeat acts (a) through (d) if said measured parameter does not have a predetermined relationship with said predetermined reference voltage level.

6. The storage medium of claim 5, wherein said program is further configured to operate said computer to change said reference voltage level from an initial reference voltage level.

7. The storage medium of claim 5, wherein said program is further configured to operate said computer to repeat acts (a) through (d) if a measured voltage is not less than said predetermined reference voltage level.

8. The storage medium of claim 7, wherein said program is further configured to operate said computer to repeat acts (a) through (d) if a voltage measured at a ground terminal is not less than said predetermined reference voltage level.

9. The storage medium of claim 5, wherein said program is further configured to operate said computer to repeat acts (a) through (d) if a measured voltage is not less than said predetermined reference voltage level.

10. The storage medium of claim 9, wherein said program is further configured to operate said computer to repeat acts (a) through (d) if a voltage measured at a power rail of said circuit under test is not less than said predetermined reference voltage level.

11. The storage medium of claim 1, wherein said program is further configured to operate said computer to disconnect said test circuit from a power rail of said circuit under test.

12. The storage medium of claim 11, wherein said program is further configured to operate said computer to disconnect said test circuit from a Vdd terminal.

13. The storage medium of claim 12, wherein said program is further configured to operate said computer to toggle a state of a transistor coupled between said test circuit and said Vdd terminal.

14. The storage medium of claim 11, wherein said program is further configured to operate said computer to disconnect said test circuit from a reference voltage terminal.

15. The storage medium of claim 14, wherein said program is further configured to operate said computer to toggle a state of a transistor coupled between said test circuit and said reference voltage terminal.

16. The storage medium of claim 1, wherein said program is further configured to operate said computer to compare a sensed voltage with a reference voltage.

17. The storage medium of claim 16, wherein said program is further configured to operate said computer to compare a voltage sensed at a ground terminal of said circuit under test with a reference voltage.

18. The storage medium of claim 17, wherein said program is further configured to operate said computer to toggle a state of a transistor coupled between the test circuit and said ground terminal being sensed.

19. The storage medium of claim 16, wherein said program is further configured to operate said computer to compare a voltage sensed at a power rail of said circuit under test with a reference voltage.

20. The storage medium of claim 19, wherein said program is further configured to operate said computer to toggle a state of a transistor coupled between the test circuit and said power rail being sensed.

21. The storage medium of claim 1, wherein said program is further configured to operate said computer to quantify ground bounce for said circuit under test.

22. The storage medium of claim 1, wherein said program is further configured to operate said computer to quantify power droop of said circuit under test.

23. A processor system, comprising:

a processor; and

a communications link coupled to said processor and also coupled to a computer readable storage medium, wherein

said computer readable storage medium stores a computer program for measuring a parameter of a circuit under test, said computer program configured to operate said processor to;

(a) charge a first portion of a test circuit up to a first voltage level;

(b) charge a second portion of said test circuit up to a second voltage level;

(c) disconnect said test circuit from respective voltage terminals providing said first and second voltage levels; and

(d) measure said parameter of said circuit under test with said test circuit.

24. The processor system of claim 23, wherein said program is further configured to operate said processor to charge a first capacitor of said test circuit to a power rail voltage level, and also to charge a second capacitor of said test circuit to a predetermined reference voltage level.

25. The processor system of claim 24, wherein said program is further configured to operate said processor to charge said first capacitor to Vdd.

26. The processor system of claim 24, wherein said program is further configured to operate said processor to charge said second capacitor to an initial reference voltage level.

27. The processor system of claim 24, wherein said program is further configured to operate said processor to:

change said predetermined reference voltage level; and

repeat acts (a) through (d) if said measured parameter does not have a predetermined relationship with said predetermined reference voltage level.

28. The processor system of claim 27, wherein said program is further configured to operate said processor to change said reference voltage level from an initial reference voltage level.

29. The processor system of claim 27, wherein said program is further configured to operate said processor to repeat acts (a) through (d) if a measured voltage is not less than said predetermined reference voltage level.

30. The processor system of claim 29, wherein said program is further configured to operate said processor to repeat acts (a) through (d) if a voltage measured at a ground terminal is not less than said predetermined reference voltage level.

31. The processor system of claim 27, wherein said program is further configured to operate said processor to repeat acts (a) through (d) if a measured voltage is not less than said predetermined reference voltage level.

32. The processor system of claim 31, wherein said program is further configured to operate said processor to repeat acts (a) through (d) if a voltage measured at a power rail of said circuit under test is not less than said predetermined reference voltage level.

33. The processor system of claim 23, wherein said program is further configured to operate said processor to disconnect said test circuit from a power rail of said circuit under test.

34. The processor system of claim 33, wherein said program is further configured to operate said processor to disconnect said test circuit from a Vdd terminal.

35. The processor system of claim 34, wherein said program is further configured to operate said processor to toggle a state of a transistor coupled between said test circuit and said Vdd terminal.

36. The processor system of claim 33, wherein said program is further configured to operate said processor to disconnect said test circuit from a reference voltage terminal.

37. The processor system of claim 36, wherein said program is further configured to operate said processor to toggle a state of a transistor coupled between said test circuit and said reference voltage terminal.

38. The processor system of claim 23, wherein said program is further configured to operate said processor to compare a sensed voltage with a reference voltage.

39. The processor system of claim 38, wherein said program is further configured to operate said processor to compare a voltage sensed at a ground terminal of said circuit under test with a reference voltage.

40. The processor system of claim 39, wherein said program is further configured to operate said processor to toggle a state of a transistor coupled between the test circuit and said ground terminal being sensed.

41. The processor system of claim 38, wherein said program is further configured to operate said processor to compare a voltage sensed at a power rail of said circuit under test with a reference voltage.

42. The processor system of claim 41, wherein said program is further configured to operate said processor to toggle a state of a transistor coupled between the test circuit and said power rail being sensed.

43. The processor system of claim 23, wherein said program is further configured to operate said processor to quantify ground bounce for said circuit under test.

44. The processor system of claim 23, wherein said program is further configured to operate said processor to quantify power droop of said circuit under test.