Fast and accurate adjustment of gain and exposure time for image sensors

• US 6,947,077 B1
• Filed: 03/30/1999
• Issued: 09/20/2005
• Est. Priority Date: 03/30/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Krymski, Alexander I.
• Primary Examiner(s): Groody, James J.
• Assistant Examiner(s): Tran, Nhan
• Application Number:
  US09/281,765
• Time in Patent Office: 2,366 Days
• Field of Search: 348/221.1, 348/222.1, 348294-298, 348/221, 348/222, 348/229, 348362-367, 377/16, 377/20, 377/33, 377/49, 377/53, 377/107, 377/108, 377/45, 377/116
• US Class Current: 348/222.1
• CPC Class Codes: H03K 21/38 Starting, stopping or resetting the counter counters with a base other than a power of two H03K23/48, H03K23/66
• CPC Class Codes: H04N 23/73 by influencing the exposure time

Abstract

A proportional counting circuit generates count values for use in variably adjusting gain and exposure time of an image sensor array. The count values are adjusted in proportion to the current count value. This technique allows for fast and accurate adjustment of gain and exposure time without sacrificing the visual performance defined by the contrast difference. At least one break-in signal disables counting in some lower bits when a particular higher bit is asserted and allows the count values to be adjusted by a different increment when the count value reaches a predetermined value by asserting the particular higher bit. Break-out signals are used in less significant bits to disable counting in all lower bits than the bit being disabled by the break-in signal from the more significant bit.

Claims

1. A N-bit proportional bit counting circuit comprising:

N counter cells, at least M of said counter cells comprising,

(a) a first input element that receives a plurality of independent break-in signals to change a counting operation; and

(b) a bit processing element coupled to the first input element and configured to receive a clock signal and further configured to, on each pulse of said clock signal;

(1) enable counting if all of the break-in signals are de-asserted; and

(2) disable counting if at least one of the break-in signals is asserted;

wherein

N is an integer greater than or equal to 3,

M is an integer greater than or equal to 2 and less than N,

said M counter cells form a sequence of adjacent bits of said counter, and

in each of said M counter cells, said first input element receives a same number of said independent break-in signals.

2. The circuit of claim 1, wherein the bit processing element includes:

(a) a second input element that receives a carry-in signal;

(b) a counting element having an input and an output, where the counting element is coupled to the second input element and configured to sum the carry-in signal and the output of the counting element; and

(c) a selection element coupled to the first input element to receive the at least one break-in signal, the selection element also coupled to the counting element and configured to;

(1) hold the counting element in an idle state if the at least one break-in signal is asserted; and

(2) command the counting element to latch the computed sum if each of break-in signals is de-asserted.

3. The circuit of claim 2, wherein the bit processing element also includes a second selection element coupled to the first input element and the counting element, the second selection element configured to generate a carry-out signal, where the carry-out signal is a carry out from the sum computed in the counting element.

4. The circuit of claim 2, wherein the bit processing element further includes an output element that generates a break-out signal, where the break-out signal is asserted if at least one of the at least one break-in signal is asserted and the break-out signal is de-asserted if all of the at least one break-in signal are de-asserted.

5. A proportional bit counting circuit comprising:

a plurality of counter cells, at least one of said counter cells comprising,

(a) a first input element that receives a plurality of independent break-in signals to change a counting operation;

(b) a second input element that receives a carry-in signal;

(c) a counting element having a clock input, a signal input, and an output, where the counting element is coupled to the first and second input elements and configured to;

receive a clock signal on said clock input, and,

on each pulse of said clock signal,

enable counting if all of the break-in signals are de-asserted;

disable counting if at least one of the break-in signals is asserted; and

sum the carry-in signal and the output of the counting element.

6. The circuit of claim 5, further comprising a second selection element coupled to the first input element and the counting element, the second selection element configured to generate a carry-out signal, where the carry-out signal is a carry out from the sum computed in the counting element.

7. The circuit of claim 5, further comprising a third input element that receives a down-up signal indicating whether to count down or count up and coupled to the counting element, the counting element configured to sum the down-up signal with the carry-in signal and the output of the counting element.

8. The circuit of claim 7, further comprising a second selection element coupled to the input elements and the counting element, the second selection element configured to generate a carry-out signal, where the carry-out signal is:

(a) an inverted down-up signal if the break-in signal is asserted; and

(b) a carry out from the sum computed in the counting element if the break-in signal is de-asserted.

9. The circuit of claim 5, wherein the counting element includes:

(a) a latch circuit that changes the output according to the input, the latch circuit capable of being configured into an idle state when the output is fed directly back into the input; and

(b) an adding circuit that computes a binary sum of the input.

10. A proportional bit counting circuit comprising:

a plurality of counter cells, at least one of said counter cells comprising,

(a) a first input element that receives a plurality of independent break-in signals;

(b) a second input element that receives a carry-in signal;

(c) a latching element having a clock input, a signal input, and an output;

(d) a summing element coupled to the second input element and configured to sum the carry-in signal and the output of the latching element; and

(e) a selection element coupled to the first input element to receive the break-in signals, the selection element also coupled to the summing element and the latching element to, on each pulse of a clock signal received on said clock input,

(1) hold a counting element in an idle state if at least one of the plurality of break-in signals is asserted; and

(2) command the counting element to latch the computed sum if each of the the plurality of break-in signals is de-asserted.

11. The circuit of claim 10, further comprising an output element that generates a break-out signal, where the break-out signal is asserted if at least one of the at least one break-in signal is asserted and the break-out signal is de-asserted if all of the at least one break-in signal are de-asserted.

12. The circuit of claim 10, further comprising a second selection element coupled to the first input element and the counting element, the second selection element configured to generate a carry-out signal, where the carry-out signal is a carry out from the sum computed in the counting element.

13. A proportional counting circuit having a count value and for use in adjusting gains and integration times of an image sensor array, the circuit comprising:

(a) an input clock element that receives a clock signal;

(b) a plurality, N, of bit counting circuits coupled to the input clock element and configured to count by an increment proportional to the count value and triggered by the clock signal, at least M of the circuits comprising;

(1) an input element that receives carry-in signals and a plurality of independent break-in signals;

(2) a plurality of bit processing elements coupled to the input element and configured to, on each pulse of the clock signal,

(a) enable bit counting and output a bit count if all of the plurality of break-in signals are de-asserted; and

(b) disable bit counting if at least one of the break-in signals is asserted;

(3) an output element that generates the count value by collecting bit counts and carry-out signals from the plurality of bit counting circuits;

wherein

N is an integer greater than or equal to 3,

M is an integer greater than or equal to 2 and less than N,

said M counter cells form a sequence of adjacent bits, and

in each of said M counter cells, said input element receives a same number of said independent break-in signals.

14. The circuit of claim 13, wherein the bit counting is enabled in the plurality of bit processing elements by adding the carry-in signal with a previous bit count value.

15. The circuit of claim 13, wherein the bit counting is disabled in the plurality of bit processing elements by feeding a previous bit count value back to an input of the bit processing element, where the bit processing element is placed in an idle state, and the bit processing element generating carry-out signal.

16. A method for counting, where a count increment is varied proportional to the count value, for use in adjusting gains and integration times of an image sensor array, the method comprising:

(a) receiving a clock signal;

(b) on each pulse of said clock signal;

(1) sending a same plurality of independent break-in signals to a lower bit counter when a higher bit counter is asserted, such that the lower bit counter is disabled from counting, and the count increment and the count value are proportionally adjusted; and

(2) outputting the adjusted count value.

17. The method of claim 16, wherein the lower bit counter is disabled by feeding a previous bit count value back to an input of the lower bit counter, where the lower bit counter is placed in an idle state.

18. The method of claim 16, further comprising generating carry-out signal when the lower bit counter is disabled from counting.

19. An image sensor system that converts an optical image into a digital image, the system comprising:

(a) an image sensor array including;

(1) a plurality of photodetectors to convert photos impinging on the photodetectors to electric charges; and

(2) an electronic circuitry to integrate the electric charges to analog voltages;

(b) a timing and control circuitry coupled to the image sensor array and configured to variably adjust the integration time of the electric charge to analog voltages;

(c) an analog-to-digital converter coupled to the image sensor array to convert the analog voltages to digital voltages representing a digital image;

wherein said timing and control circuitry includes a N-bit proportional counter, said counter comprising N cells, at least M of said cells receiving a clock signal and a plurality of independent break-in signals and including control circuitry configured to, on each pulse of the clock signal, disable counting if at least one break-in signal is asserted, and

wherein

N is an integer greater than or equal to 3,

M is an integer greater than or equal to 2 and less than N,

said M counter cells form a sequence of adjacent bits of said counter, and

in each of said M counter cells, said first input element receives a same number of said independent break-in signals.

20. The system of claim 19, further comprising a display device to display the digital image outputted by the analog-to-digital converter.

21. A N-bit proportional bit counting circuit comprising:

N counter cells, at least M one of said counter cells comprising,

a first input element that receives a plurality of non-complementary break-in signals to change a counting operation; and

a bit processing element coupled to the first input element and configured to receive a clock signal and further configured to, on each pulse of said clock signal;

enable counting if all of the break-in signals are de-asserted; and

disable counting if at least one of the break-in signals is asserted;

wherein

N is greater than two

M is greater than or equal to 2 and less than N,

said M counter cells form a sequence of adjacent bits of said counter, and

in each of said M counter cells, said first input element receives a same number of said non-complimentary break-in signals.

22. A proportional bit counting circuit comprising:

a plurality of counter cells, at least one of said counter cells comprising,

a first input element that receives a plurality of non-complementary break-in signals to change a counting operation;

a second input element that receives a carry-in signal;

a counting element having a clock input, a signal input, and an output, where the counting element is coupled to the first and second input elements and configured to;

receive a clock signal on said clock input, and further configured to,

on each pulse of said clock signal,

enable counting if all of the break-in signals are de-asserted;

disable counting if at least one of the break-in signals is asserted; and

sum the carry-in signal and the output of the counting elements.

23. A proportional bit counting circuit comprising:

a plurality of counter cells, at least one of said counter cells comprising,

a first input element that receives a plurality of non-complementary break-in signals;

a second input element that receives a carry-in signal;

a latching element having a clock input, a signal input, and an output;

a summing element coupled to the second input element and configured to sum the carry-in signal and the output of the latching element; and

a selection element coupled to the first input element to receive the break-in signals, the selection element also coupled to the summing element and the latching element to, on each pulse of a clock signal received on said clock input,

hold a counting element in an idle state if at least one of the plurality of break-in signals is asserted; and

command the counting element to latch the computed sum if each at least of the plurality of break-in signals is de-asserted.

24. A proportional counting circuit having a count value and for use in adjusting gains and integration times of an image sensor array, the circuit comprising:

an input clock element that receives a clock signal;

a plurality, N, of bit counting circuits coupled to the input clock element and configured to count by an increment proportional to the count value and triggered by the clock signal, at least M of the circuits comprising;

an input element that receives carry-in signals and a plurality of non-complementary break-in signals;

a plurality of bit processing elements coupled to the input element and configured to, on each pulse of the clock signal,

enable bit counting and output a bit count if all of the plurality of break-in signals are de-asserted; and

disable bit counting if at least one of the break-in signals is asserted;

an output element that generates the count value by collecting bit counts and carry-out signals from the plurality of bit counting circuits;

wherein

N is an integer greater than or equal to 3,

M is an integer greater than or equal to 2 and less than N,

said M counter cells form a sequence of adjacent bits, and

in each of said M counter cells, said input element receives a same number of said non-complimentary break-in signals.

25. A method for counting, where a count increment is varied proportional to the count value, for use in adjusting gains and integration times of an image sensor array, the method comprising:

receiving a clock signal;

on each pulse of said clock signal;

sending a same plurality of non-complementary break-in signals to a lower bit counter when a higher bit counter is asserted, such that the lower bit counter is disabled from counting, and the count increment and the count value are proportionally adjusted; and

outputting the adjusted count value.

26. An image sensor system that converts an optical image into a digital image, the system comprising:

an image sensor array including;

a plurality of photodetectors to convert photos impinging on the photodetectors to electric charges; and

an electronic circuitry to integrate the electric charges to analog voltages;

a timing and control circuitry coupled to the image sensor array and configured to variably adjust the integration time of the electric charge to analog voltages;

an analog-to-digital converter coupled to the image sensor array to convert the analog voltages to digital voltages representing a digital image;

wherein said timing and control circuitry includes a N-bit proportional counter, said counter comprising N cells, at least M of said cells receiving a clock signal and a plurality of non-complementary break-in signals and including control circuitry configured to, on each pulse of the clock signal, disable counting if at least one break-in signal is asserted, and

wherein

N is greater than three,

M is greater than or equal to 2 and less than N,

said M counter cells form a sequence of adjacent bits of said counter, and

in each of said M counter cells, said first input element receives a same number of said non-complimentary break-in signals.