Data transfer control device and electronic equipment

• US 6,947,442 B1
• Filed: 10/12/2000
• Issued: 09/20/2005
• Est. Priority Date: 10/15/1999
• Status: Expired due to Fees

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Sato, Daisuke, Horiuchi, Hiroshi
• Primary Examiner(s): Nguyen, Chau
• Assistant Examiner(s): Moore, Ian N.
• Application Number:
  US09/688,045
• Time in Patent Office: 1,804 Days
• Field of Search: 370/447, 370/446, 370/495, 370/463, 370/462, 370/489, 370/252, 370/254, 370/426, 370/429, 370/289, 370/255, 370/474, 710/107, 710112-114, 710/115, 710/116, 710/109, 710/305
• US Class Current: 370/447
• CPC Class Codes: H04L 12/40013 Details regarding a bus controller
• CPC Class Codes: H04L 12/40058 Isochronous transmission
• CPC Class Codes: H04L 12/40071 Packet processing; Packet format adaptation of digital video signals for transport over a specific network H04N21/2381, H04N21/4363, H04N21/4381; packet switches H04L49/00; intermediate storage or scheduling H04L49/90
• CPC Class Codes: H04L 12/40084 Bus arbitration

Abstract

A data transfer control device and electronic equipment that make it possible to implement high-speed data transfer with reduced overhead processing of firmware and smaller hardware. A data transfer control device that conforms to the IEEE 1394 standard comprises an arbitration circuit that permits firmware (FW) transfer after the completion of one transaction (or one packet transfer) in the continuous packet transfer, if the CPU issues an FW transfer start command during the execution of continuous hardware transfer (HW transfer) processing by a SBP-2 core. If HWStart and FWStart signals go active together, the FW transfer has priority. A header area in RAM is divided into an ordinary header area and an HW header area, and an address generation circuit switches between generating addresses for the ordinary header area and addresses for the HW header area, based on an HWDMARun signal from the arbitration circuit. A data area in RAM is divided into an ORB area and a stream area for the SBP-2 core.

Claims

1. A data transfer control device for transferring data among a plurality of nodes that are connected to a bus, the data transfer control device comprising:

a transfer execution circuit that operates when a processing section has issued a first start command which instructs continuous packet transfer by hardware, for executing processing to divide transfer data into a series of packets and transfer the thus divided series of packets continuously; and

an arbitration circuit that operates when the processing section has issued a second start command which instructs packet transfer while continuous packet transfer processing is being executed by the transfer execution circuit, for waiting until one transaction or one packet transfer in the continuous packet transfer has been completed then permitting packet transfer by the second start command;

the transfer execution circuit including at least one of;

a page table fetch circuit that operates when a page table exists in a storage memory of another node, to fetch the page table from the other node;

a page table creation circuit that operates when no page table exists in the storage memory of the other node, to create a virtual page table, based on page boundary information;

a payload division circuit for dividing transfer data into packets of a payload size;

a transfer execution control circuit for controlling the execution of data transfer; and

a control information creation circuit for creating control information of a request packet to be sent to the other node.

2. The data transfer control device as defined in claim 1, the arbitration circuit receiving a first start signal that goes active when there is a transfer start request from the transfer execution circuit, a second start signal that goes active when there is a transfer start request in accordance with the second start command, and a completion signal that goes active at transfer completion;

then causing the start of transfer processing in accordance with the first start signal when the second start signal went active after the first start signal had gone active, and causing the start of transfer processing in accordance with the second start signal after the completion signal goes active.

3. The data transfer control device as defined in claim 1, the arbitration circuit receiving a first start signal that goes active when there is a transfer start request from the transfer execution circuit, a second start signal that goes active when there is a transfer start request in accordance with the second start command, and a completion signal that goes active at transfer completion;

and giving priority to transfer processing in accordance with the second start signal when the first and second start signals have gone active together.

4. The data transfer control device as defined in claim 1, the arbitration circuit receiving a first start signal that goes active when there is a transfer start request from the transfer execution circuit, a second start signal that goes active when there is a transfer start request in accordance with the second start command, and a completion signal that goes active at transfer completion;

then causing the start of transfer processing in accordance with the second start signal when the first start signal went active after the second start signal had gone active, and causing the start of transfer processing in accordance with the first start signal after the completion signal goes active.

8. Electronic equipment comprising:

the data transfer control device as defined in claim 1;

a device for performing given processing on data that has been received from another node via the data transfer control device and the bus; and

a device for outputting or storing data that has been subjected to the processing.

11. Electronic equipment comprising:

the data transfer control device as defined in claim 1;

a device for performing given processing on data that is to be transferred to another node via the data transfer control device and the bus; and

a device for fetching data to be subjected to the processing.

14. The data transfer control device as defined in claim 1, data transfer is performed in accordance with the IEEE 1394 standard.

5. A data transfer control device for transferring data among a plurality of nodes that are connected to a bus, the data transfer control device comprising:

a transfer execution circuit that operates when a processing section has issued a first start command which instructs continuous packet transfer by hardware, for executing processing to divide transfer data into a series of packets and transfer the thus divided series of packets continuously; and

an arbitration circuit that operates when the processing section has issued a second start command which instructs packet transfer while continuous packet transfer processing is being executed by the transfer execution circuit, for waiting until one transaction or one packet transfer in the continuous packet transfer has been completed then permitting packet transfer by the second start command, the arbitration circuit performing an arbitration between the continuous packet transfer by the first start command and the packet transfer by the second start command;

randomly accessible packet storage memory having a control information area for storing packet control information and a data area for storing packet data; and

an address generation circuit which generates a write address to the packet storage memory;

the control information area of the packet storage memory being separated into a first control information area and a second control information area, control information of the second control information area being written by the transfer execution circuit; and

the address generation circuit switching between generating addresses for the first control information area and addresses for the second control information area, based on an arbitration result a result of the arbitration from the arbitration circuit.

9. Electronic equipment comprising:

the data transfer control device as defined in claim 5;

a device for performing given processing on data that has been received from another node via the data transfer control device and the bus; and

a device for outputting or storing data that has been subjected to the processing.

12. Electronic equipment comprising:

the data transfer control device as defined in claim 5;

a device for performing given processing on data that is to be transferred to another node via the data transfer control device and the bus; and

a device for fetching data to be subjected to the processing.

15. The data transfer control device as defined in claim 5, data transfer is performed in accordance with the IEEE 1394 standard.

6. A data transfer control device for transferring data among a plurality of nodes that are connected to a bus, the data transfer control device comprising:

a transfer execution circuit that operates when a processing section has issued a first start command which instructs continuous packet transfer by hardware, for executing processing to divide transfer data into a series of packets and transfer the thus divided series of packets continuously; and

an arbitration circuit that operates when the processing section has issued a second start command which instructs packet transfer while continuous packet transfer processing is being executed by the transfer execution circuit, for waiting until one transaction or one packet transfer in the continuous packet transfer has been completed then permitting packet transfer by the second start command; and

randomly accessible packet storage memory having a control information area for storing packet control information and a data area for storing packet data, the data area of the packet storage memory being separated into a first data area for storing first data for a first layer and a second data area for storing second data for a second layer, the second data being transferred by the continuous packet transfer processing of the transfer execution circuit.

7. The data transfer control device as defined in claim 6, when a request packet for starting a transaction is transmitted to another node, instruction information for instructing the processing to be performed when a response packet will be received from the other node being included within transaction identification information in the request packet;

and when a response packet is received from the other node, control information and first and second data of the response packet being respectively written to the control information area and the first and second data areas, based on the instruction information comprised within the transaction identification information in the response packet.

10. Electronic equipment comprising:

the data transfer control device as defined in claim 6;

a device for performing given processing on data that has been received from another node via the data transfer control device and the bus; and

a device for outputting or storing data that has been subjected to the processing.

13. Electronic equipment comprising:

the data transfer control device as defined in claim 6;

a device for performing given processing on data that is to be transferred to another node via the data transfer control device and the bus; and

a device for fetching data to be subjected to the processing.

16. The data transfer control device as defined in claim 6, data transfer is performed in accordance with the IEEE 1394 standard.