Stream cipher having a shuffle network combiner function
First Claim
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1. An apparatus comprising:
- at least one data bit generator to generate a first, second and third plurality of data bits; and
a combiner function, coupled to the at least one data bit generator, including a network of shuffle units, to combine the third plurality of data bits, using the first and second plurality of data bits as first input data bits and control signals respectively of the network of shuffle units.
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Abstract
A stream cipher is provided with one or more data bit generators to generate a first, second and third set of data bits. The stream cipher is further provided with a combiner function having a network of shuffle units to combine the third set of data bits, using the first and second sets of data bits as first input data bits and control signals respectively of the network of shuffle units. In one embodiment, the shuffle units are binary shuffle units and they are serially coupled to one another.
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Citations
29 Claims
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1. An apparatus comprising:
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at least one data bit generator to generate a first, second and third plurality of data bits; and
a combiner function, coupled to the at least one data bit generator, including a network of shuffle units, to combine the third plurality of data bits, using the first and second plurality of data bits as first input data bits and control signals respectively of the network of shuffle units. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. An apparatus comprising:
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a first XOR gate to receive a first plurality of data bits and combine them into a second data bit;
a network of shuffle units, coupled to the first XOR gate, to output a third data bit by shuffling and propagating the second data bit through the network of shuffle units under the control of a fourth plurality of data bits; and
a second XOR gate coupled to the network of shuffle units to combine a fifth plurality of data bits using the third data bit;
wherein at least one of the shuffle units comprises a first and a second flip-flop to store a first and a second state value, and a plurality of selectors coupled to the first and second flip- flops to control selective output of one of the first and second state values based on a corresponding one of said fourth plurality of data bits. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. A hardware implemented method using a network of shuffle units comprising:
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generating a first, second and third plurality of data bits; and
shuffling and propagating a fourth data bit generated from the first plurality of data bits, under the control of the second plurality of data bits, to output a fifth data bit to combine the third plurality of data bits. - View Dependent Claims (28, 29)
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Specification