Optical waveguides formed from nano air-gap inter-layer dielectric materials and methods of fabrication thereof

• US 6,947,651 B2
• Filed: 05/10/2002
• Issued: 09/20/2005
• Est. Priority Date: 05/10/2001
• Status: Expired due to Fees

• Current Assignee: Georgia Tech Research Corporation (University System of Georgia)
• Original Assignee: Georgia Tech Research Corporation (University System of Georgia)
• Inventors: Allen, Sue Ann B., Padovani, Agnes, Gaylord, Thomas K., Meindl, James D., Kohl, Paul, Mule′, Tony, Glytsis, Elias N.
• Primary Examiner(s): Williams, Joseph
• Assistant Examiner(s): MACCHIAROLO, PETER J
• Application Number:
  US10/142,601
• Publication Number:
  US 20020186950A1
• Time in Patent Office: 1,229 Days
• Field of Search: 385124-129
• US Class Current: 385/125
• CPC Class Codes: G02B 2006/12104 Mirror; Reflectors or the like
• CPC Class Codes: G02B 6/124 Geodesic lenses or integrated gratings
• CPC Class Codes: G02B 6/13 Integrated optical circuits characterised by the manufacturing method
• CPC Class Codes: G02B 6/138 by using polymerisation

Abstract

Waveguides and methods of fabrication thereof are presented. A representative waveguide includes a waveguide core and a cladding layer, where the cladding layer surrounds the waveguide core. The waveguide core and cladding can be made of a host material having a plurality of nano-pores, wherein the nano-pores include a sacrificial material, and the sacrificial material can be selectively decomposed in both the core and cladding layers to form a plurality of nano air-gaps.

Claims

1. A waveguide, comprising:

a waveguide core made of a first host material having a plurality of nano-pores, wherein the nano-pores include a sacrificial material, wherein the sacrificial material has a decomposition temperature less than a decomposition temperature of the first host material, wherein the decomposition temperature of the sacrificial material is greater than the cure temperature of the first host material; and

a cladding layer made of a second host material having a plurality of nano air-gaps, wherein the cladding layer is disposed around the waveguide core.

2. The waveguide of claim 1, wherein the first host material and the second host material comprise the same host material.

3. The waveguide of claim 1, wherein the first host material and the second host material comprise different host materials.

4. The waveguide of claim 1, wherein the nano-pores include a first amount of the sacrificial material so that the cladding layer has a lower refractive index than the waveguide core.

5. The waveguide of claim 1, wherein the nano air-gaps include a second amount of the sacrificial material so that the cladding layer has a lower refractive index than the waveguide core.

6. The waveguide of claim 1, wherein the first host material and the second host material are selected from methylsilsesquixane and polyimides.

7. The waveguide of claim 1, wherein the first host material and the second host material includes methylsilsesquixane.

8. The waveguide of claim 1, wherein the sacrificial material is chosen from trimethoxysilye norborene, polynorbornenes, polyoxymethylene, polycarbonates, polyethers, and polyesters.

9. The waveguide of claim 1, wherein the nano air-gaps have a diameter of about 1 to about 15 nanometers.

10. The waveguide of claim 1, further comprising at least one coupler element.

11. The waveguide of claim 1, wherein the sacrificial material includes mesitylene.

12. A device, comprising:

a substrate; and

a waveguide disposed on the substrate, wherein the waveguide includes;

a waveguide core made of a material having a plurality of nano-pores, wherein the nano-pores include a sacrificial material, wherein the sacrificial material has a decomposition temperature less than a decomposition temperature of the first host material, wherein the decomposition temperature of the sacrificial material is greater than the cure temperature of the first host material; and

a cladding layer made of the material having a plurality of nano air-gaps.

13. The device of claim 12, wherein the substrate is selected from a complementary metal oxide semiconductor wafer, compound semiconductor wafer, a fully processed semiconductor substrate, a partially processed semiconductor substrate, a dielectric substrate, a printed wiring board, a multi-chip module, fused silica, and a backplane substrate.