High-performance, superscalar-based computer system with out-of-order instruction execution

• US 6,948,052 B2
• Filed: 10/29/2002
• Issued: 09/20/2005
• Est. Priority Date: 07/08/1991
• Status: Expired due to Fees

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Wang, Johannes, Wang, Sze-Shun, Nguyen, Le Trong, Miyayama, Yoshiyuki, Trang, Quang H., Lau, Te-Li, Garg, Sanjiv, Lentz, Derek J., Hagiwara, Yasuaki
• Primary Examiner(s): PAN, DANIEL H
• Application Number:
  US10/282,207
• Publication Number:
  US 20030079113A1
• Time in Patent Office: 1,057 Days
• Field of Search: 712/207, 712/213, 712/233, 712/206, 712/245, 712/212, 712/237, 711/125, 711/123
• US Class Current: 712/207
• CPC Class Codes: G06F 9/30061 Multi-way branch instructions, e.g. CASE
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/30116 Shadow registers, e.g. coupled registers, not forming part of the register space
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/327 for interrupts
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3804 for branches, e.g. hedging, branch folding
• CPC Class Codes: G06F 9/3806 using address prediction, e.g. return stack, branch history buffer
• CPC Class Codes: G06F 9/3822 Parallel decoding, e.g. parallel decode units
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 : Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3863 : using multiple copies of the architectural state, e.g. shadow registers
• CPC Class Codes: G06F 9/3865 : using deferred exception handling, e.g. exception flags
• CPC Class Codes: G06F 9/3885 : using a plurality of independent parallel functional units

Abstract

A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Claims

1. A microprocessor, comprising:

an instruction fetch unit, including

a prefetch buffer comprising a plurality of storage locations, each of said plurality of storage locations adapted to store an instruction set comprising a plurality of instructions;

prefetch control logic that issues a plurality of requests to an instruction store in a predetermined order, each of said plurality of requests including a unique identifier, and stores a plurality of instruction sets returned from said instruction store in said prefetch buffer, each of said plurality of instruction sets corresponding to a respective one of said plurality of requests, wherein said prefetch control logic associates each of said plurality of instruction sets with a unique identifier from said corresponding one of said plurality of requests, and wherein said prefetch control logic stores at least one of said plurality of instruction sets in said prefetch buffer out-of-order with respect to said predetermined order;

a branch decoder that decodes said plurality of instruction sets in an order specified by said unique identifiers associated with said plurality of instruction sets, wherein said order specified by said unique identifiers associated with said plurality of instruction sets is consistent with said predetermined order; and

a first in first out (FIFO) buffer that receives and stores said plurality of instruction sets decoded by said branch decoder in the order in which said plurality of instruction sets was decoded; and

an instruction execution unit that receives and executes said plurality of instruction sets stored in said FIFO buffer.

2. The microprocessor of claim 1, wherein said prefetch buffer comprises:

a first set of storage locations for storing instruction sets corresponding to a first instruction stream and a second set of storage locations for storing instruction sets corresponding to a second instruction stream.

3. The microprocessor of claim 2, wherein said branch decoder outputs a control signal to said prefetch control logic in response to decoding a branch instruction in one of said plurality of instruction sets, and wherein said prefetch control logic stores further instruction sets returned from said instruction store in either said first set of storage locations or said second set of storage locations in said prefetch buffer dependent upon said control signal.

4. The microprocessor of claim 2, wherein said prefetch buffer further comprises:

a third set of storage locations for storing instruction sets corresponding to a third instruction stream.

5. The microprocessor of claim 1, further comprising:

a bus that permits instruction sets to be provided directly from said instruction store to said branch decoder, thereby bypassing said prefetch buffer.

6. The microprocessor of claim 1, wherein said prefetch control logic includes:

a counter for generating said unique identifiers.

7. The microprocessor of claim 6, wherein said counter comprises a circular counter.

8. The microprocessor of claim 1, further comprising:

a status array including a plurality of status storage locations, each of said plurality of status storage locations logically corresponding to a respective storage location in said prefetch buffer,

wherein said prefetch control logic stores each of said unique identifiers in a status storage location that logically corresponds to the storage location in said prefetch buffer in which an associated one of said plurality of instruction sets is stored.

9. The microprocessor of claim 1, further comprising:

buffer control logic that serially transfers each of said plurality of instruction sets from a top portion of said FIFO buffer to a bottom portion of said FIFO buffer;

wherein said execution unit receives and executes instruction sets from said bottom portion of said FIFO buffer.

10. The microprocessor of claim 9, wherein said bottom portion of said FIFO buffer comprises two registers.

11. The microprocessor of claim 1, wherein each of said plurality of instruction sets comprises four instructions.

12. The microprocessor of claim 1, wherein said prefetch buffer stores each instruction in each of said plurality of instruction sets in parallel.

13. The microprocessor of claim 1, wherein said branch decoder decodes each instruction in each of said plurality of instruction sets in parallel.

14. A microprocessor, comprising:

an instruction fetch unit, including

a prefetch buffer comprising a plurality of storage locations, each of said plurality of storage locations adapted to store an instruction set comprising a plurality of instructions;

prefetch control logic that issues a plurality of requests to an instruction store in a predetermined order, each of said plurality of requests including a unique identifier, and stores a plurality of instruction sets returned from said instruction store in said prefetch buffer, each of said plurality of instruction sets corresponding to a respective one of said plurality of requests, wherein said prefetch control logic associates each of said plurality of instruction sets with a unique identifier from said corresponding one of said plurality of requests, and wherein said prefetch control logic stores at least one of said plurality of instruction sets in said prefetch buffer out-of-order with respect to said predetermined order;

a branch decoder that decodes said plurality of instruction sets in an order specified by said unique identifiers associated with said plurality of instruction sets, wherein said order specified by said unique identifiers associated with said plurality of instruction sets is consistent with said predetermined order; and

a buffer that receives and stores said plurality of instruction sets decoded by said branch decoder in the order in which said plurality of instruction sets was decoded; and

an instruction execution unit that receives and executes said plurality of instruction sets after storage in said buffer.

15. The microprocessor of claim 14, wherein said prefetch buffer comprises:

a first set of storage locations for storing instruction sets corresponding to a first instruction stream and a second set of storage locations for storing instruction sets corresponding to a second instruction stream.

16. The microprocessor of claim 15, wherein said branch decoder outputs a control signal to said prefetch control logic in response to decoding a branch instruction in one of said plurality of instruction sets, and wherein said prefetch control logic stores further instruction sets returned from said instruction store in either said first set of storage locations or said second set of storage locations in said prefetch buffer dependent upon said control signal.

17. The microprocessor of claim 15, wherein said prefetch buffer further comprises:

a third set of storage locations for storing instruction sets corresponding to a third instruction stream.

18. The microprocessor of claim 14, further comprising;

a bus that permits instruction sets to be provided directly from said instruction store to said branch decoder, thereby bypassing said prefetch buffer.

19. The microprocessor of claim 14, wherein said prefetch control logic includes:

a counter for generating said unique identifiers.

20. The microprocessor of claim 19, wherein said counter comprises a circular counter.

21. The microprocessor of claim 14, further comprising:

a status array including a plurality of status storage locations, each of said plurality of status storage locations logically corresponding to a respective storage location in said prefetch buffer,

wherein said prefetch control logic stores each of said unique identifiers in a status storage location that logically corresponds to the storage location in said prefetch buffer in which an associated one of said plurality of instruction sets is stored.

22. The microprocessor of claim 14, further comprising:

buffer control logic that serially transfers each of said plurality of instruction sets from a top portion of said buffer to a bottom portion of said buffer;

wherein said execution unit receives and executes instruction sets from said bottom portion of said buffer.

23. The microprocessor of claim 22, wherein said bottom portion of said buffer comprises two registers.

24. The microprocessor of claim 14, wherein each of said plurality of instruction sets comprises four instructions.

25. The microprocessor of claim 14, wherein said prefetch buffer stores each instruction in each of said plurality of instruction sets in parallel.

26. The microprocessor of claim 14, wherein said branch decoder decodes each instruction in each of said plurality of instruction sets in parallel.

27. A computer system, comprising:

a microprocessor;

a memory;

a bus coupling said microprocessor to said memory, said microprocessor comprising;

an instruction fetch unit, including

a prefetch buffer comprising a plurality of storage locations, each of said plurality of storage locations adapted to store an instruction set comprising a plurality of instructions;

prefetch control logic that issues a plurality of requests to an instruction store in a predetermined order, each of said plurality of requests including a unique identifier, and stores a plurality of instruction sets returned from said instruction store in said prefetch buffer, each of said plurality of instruction sets corresponding to a respective one of said plurality of requests, wherein said prefetch control logic associates each of said plurality of instruction sets with a unique identifier from said corresponding one of said plurality of requests, and wherein said pre fetch control logic stores at least one of said plurality of instruction sets in said prefetch buffer out-of-order with respect to said predetermined order;

a branch decoder that decodes said plurality of instruction sets in an order specified by said unique identifiers associated with said plurality of instruction sets, wherein said order specified by said unique identifiers associated with said plurality of instruction sets is consistent with said predetermined order; and

a buffer that receives and stores said plurality of instruction sets decoded by said branch decoder in the order in which said plurality of instruction sets was decoded; and

an instruction execution unit that receives and executes said plurality of instruction sets after storage in said buffer.

28. The system of claim 27, wherein said prefetch buffer comprises:

a first set of storage locations for storing instruction sets corresponding to a first instruction stream and a second set of storage locations for storing instruction sets corresponding to a second instruction stream.

29. The system of claim 28, wherein said branch decoder outputs a control signal to said prefetch control logic in response to decoding a branch instruction in one of said plurality of instruction sets, and wherein said prefetch control logic stores further instruction sets returned from said instruction store in either said first set of storage locations or said second set of storage locations in said prefetch buffer dependent upon said control signal.

30. The system of claim 28, wherein said prefetch buffer further comprises:

a third set of storage locations for storing instruction sets corresponding to a third instruction stream.

31. The system of claim 27, further comprising:

a bus that permits instruction sets to be provided directly from said instruction store to said branch decoder, thereby bypassing said prefetch buffer.

32. The system of claim 27, wherein said prefetch control logic includes:

a counter for generating said unique identifiers.

33. The system of claim 32, wherein said counter comprises a circular counter.

34. The system of claim 27, further comprising:

a status array including a plurality of status storage locations, each of said plurality of status storage locations logically corresponding to a respective storage location in said prefetch buffer,

wherein said prefetch control logic stores each of said unique identifiers in a status storage location that logically corresponds to the storage location in said prefetch buffer in which an associated one of said plurality of instruction sets is stored.

35. The system of claim 27, further comprising:

buffer control logic that serially transfers each of said plurality of instruction sets from a top portion of said buffer to a bottom portion of said buffer;

wherein said execution unit receives and executes instruction sets from said bottom portion of said buffer.

36. The system of claim 35, wherein said bottom portion of said buffer comprises two registers.

37. The system of claim 27, wherein each of said plurality of instruction sets comprises four instructions.

38. The system of claim 27, wherein said prefetch buffer stores each instruction in each of said plurality of instruction sets in parallel.

39. The system of claim 27, wherein said branch decoder decodes each instruction in each of said plurality of instruction sets in parallel.