Memory modules storing therein boot codes and method and device for locating same

• US 6,948,057 B2
• Filed: 04/02/2002
• Issued: 09/20/2005
• Est. Priority Date: 02/08/2002
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Tsai, Jih-Hsin, Huang, Hsiang-I, Lai, Jiin
• Primary Examiner(s): Butler, Dennis M.
• Application Number:
  US10/114,519
• Publication Number:
  US 20030154370A1
• Time in Patent Office: 1,267 Days
• Field of Search: 713/1, 713/2, 713/100
• US Class Current: 713/2
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57

Abstract

A memory module storing therein boot codes, a core logic device capable of distinguishing such memory module from the other memory modules of the same module specification, and a method for realizing the boot codes from the memory module storing therein the boot codes are disclosed. All the memory modules are electrically connected to the core logic device via respective signal pins, but the memory module storing therein boot codes outputs an identifying signal different from the identifying signals outputted by the other memory modules in a booting process. Therefore, the core logic device can locate the memory module storing therein the boot codes, and the host device can accomplish the booting process by reading the boot codes from the specific memory module.

Claims

1. A memory module electrically connected to a core logic device of a computer system via a point-to-point signal pin, storing therein boot codes required for booting said computer system, and outputting an identifying signal to said core logic device of said computer system via said point-to-point signal pin to inform of the presence of said booting codes therein.

2. The memory module according to claim 1 wherein said point-to-point signal pin is selected from a group consisting of a chip select pin and a clock enable pin.

3. The memory module according to claim 1 comprising a pull-down resistor electrically connected to said point-to-point signal pin for outputting said identifying signal as a low-level digital signal.

4. The memory module according to claim 1 comprising a pull-up resistor electrically connected to said point-to-point signal pin for outputting said identifying signal as a high-level digital signal.

5. The memory module according to claim 1 wherein said core logic device is a north-bridge chip.

6. The memory module according to claim 1 wherein said identifying signal is outputted to said core logic device of said computer system in a booting process of said computer system.

7. The memory module according to claim 1 comprising a non-volatile memory for storing said boot codes.

8. A core logic device of a host device, electrically connected via respective point-to-point signal pins to a plurality of memory modules, a specific one of which stores therein boot codes required for booting said host device, receiving identifying signals from said plurality of memory modules via said point-to-point signal pins, respectively, and locating said specific memory module storing therein said boot codes according to said identifying signals.

9. The core logic device according to claim 8 wherein said point-to-point signal pins are selected from a group consisting of chip select pins and clock enable pins.

10. The core logic device according to claim 8 wherein one of said point-to-point signal pins is electrically connected to a pull-down resistor of said specific memory module storing said boot codes to receive a corresponding one of said identifying signals as a low-level digital signal, and the other point-to-point signal pins are electrically connected to respective pull-up resistors to receive all the other identifying signals as high-level digital signals, thereby locating said specific memory module storing therein said boot codes.

11. The core logic device according to claim 8 wherein one of said point-to-point signal pins is electrically connected to a pull-up resistor of said specific memory module storing said boot codes to receive a corresponding one of said identifying signals as a high-level digital signal, and the other point-to-point signal pins are electrically connected to respective pull-down resistors to receive all the other identifying signals as low-level digital signals, thereby locating said specific memory module storing therein said boot codes.

12. The core logic device according to claim 8 being a chipset.

13. The core logic device according to claim 8 being a north-bridge chip.

14. The core logic device according to claim 8 wherein said specific memory module is a non-volatile memory module, and the other memory modules are random access memory modules.

15. A method for realizing boot codes from a memory module set, said memory module set including a plurality of memory modules electrically connected to a core logic device via respective signal pins, a specific one of said memory modules storing therein said boot codes exclusively includes a first-level-state pulling resistor coupled to a corresponding one of said signal pins, and said method comprising steps of:

said core logic device receiving identifying signals from said memory modules via said respective signal pins in a booting process, wherein one of said identifying signals received from said specific one of said memory modules is exclusively at said first level state;

said core logic device determining which one of said memory modules is said specific memory module that stores therein said boot codes by locating the exclusive one of said identifying signals at said first level state; and

allowing said boot codes to be read out from said memory module storing therein said boot codes.

16. The method according to claim 15 wherein said signal pins are point-to-point signal pins.

17. The method according to claim 16 wherein said point-to-point signal pins are selected from a group consisting of chip select pins and clock enable pins.

18. The method according to claim 15 wherein said first level state is a low-level state, and all the other identifying signals received by said core logic device are at a high-level state.

19. The method according to claim 15 wherein said first level state is a high-level state, and all the other identifying signals received by said core logic device are at a low-level state.

20. The method according to claim 15 wherein said core logic device is a chipset.

21. The method according to claim 15 wherein said core logic device is a north-bridge chip.

22. The method according to claim 15 wherein said memory module for storing said boot codes is a non-volatile memory module, and the other memory modules are random access memory modules.