Method and apparatus for providing supply voltages for a processor

• US 6,948,079 B2
• Filed: 12/26/2001
• Issued: 09/20/2005
• Est. Priority Date: 12/26/2001
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Nguyen, Don J., Lenehan, Daniel J., Zhang, Kevin X.
• Primary Examiner(s): Browne, Lynne H.
• Assistant Examiner(s): Patel, Nitin C.
• Application Number:
  US10/033,406
• Publication Number:
  US 20030120958A1
• Time in Patent Office: 1,364 Days
• Field of Search: 713/300, 713/320, 713/322, 713/323, 713/324, 713/330, 713/310
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

For one embodiment of the present invention, a processor may include one or more integrated voltage regulators powered by an external voltage regulator and generating one or more local supply voltages for the processor. The one or more local supply voltages may be set to allow one or more circuits powered by the local supply voltage(s) to meet a timing requirement. The local supply voltage(s) may be adjusted by the processor in accordance with a power management policy.

Claims

1. A processor comprising:

a first functional unit to execute a first stream of instructions;

a second functional unit to execute a second stream of instructions;

a first local voltage, regulator to provide a first local supply voltage to the first functional unit, said first local voltage regulator to reduce the first local supply voltage based at least in part on a gap between instructions in the first stream of instructions;

a second local voltage regulator to provide a second local supply voltage to the second functional unit, said second local voltage regulator to reduce the second local supply voltage based at least in part on a gap between instructions in the second stream of instructions; and

a global power grid to power the first and second local voltage regulators with a global supply voltage.

2. The processor of claim 1, wherein at least one of the first and second local supply voltages is adjustable by the processor.

3. The processor of claim 2, wherein at least one of the first and second voltage regulators includes a digitized resistor to be set by the processor.

4. The processor of claim 1, wherein at least one of the first and second local supply voltages is to be set to allow the respective functional unit to meet a timing requirement.

5. The processor of claim 1, further comprising a port to receive the global supply voltage from an external voltage regulator.

6. The processor of claim 1, wherein at least one of the first and second local voltage regulators includes an op amp.

7. The processor of claim 1, wherein the first functional unit is selected from a group comprising a branch prediction unit, a floating point unit, and an integer unit.

8. A computer system comprising:

a discrete voltage regulator to provide a global supply voltage; and

a processor including

a first functional unit to execute a first stream of instructions;

a second functional unit to execute a second stream of instructions;

a first local voltage regulator to provide a first local supply voltage to the first functional unit, said first local voltage regulator to reduce the first local supply voltage based at least in part on a gap between instructions in the first stream of instructions;

a second local voltage regulator to independently provide a second local supply voltage to the second functional unit, said second local voltage regulator to reduce the second local supply voltage based at least in part on a gap between instructions in the second stream of instructions; and

a global power grid to power the first and second local voltage regulators with the global supply voltage.

9. The computer system of claim 8, wherein at least one of the first and second local supply voltages is adjustable by the processor.

10. The computer system of claim 9, wherein at least one of the first and second local voltage regulators includes a digitized resistor to be set by the processor.

11. The computer system of claim 8, wherein the processor is a graphics controller.

12. A method comprising:

providing a global supply voltage to a first local voltage regulator and a second local voltage regulator in a processor;

providing a first local supply voltage from the first local voltage regulator to a first functional unit to execute a first stream of instructions;

reducing the first local supply voltage based at least in part on a gap between instructions in the first stream of instructions;

providing a second local supply voltage from the second local voltage regulator to a second functional unit to execute a second stream of instructions; and

reducing the second local supply voltage based at least in part on a gap between instructions in the second stream of instructions.

13. The method of claim 12, wherein providing the first local supply voltage comprises:

adjusting the first local supply voltage by the processor.

14. The method of claim 12, wherein the first functional unit comprises a floating point unit of the processor, and wherein providing the first local supply voltage comprises powering the floating point unit.