High integrity recovery from multi-bit data failures

• US 6,948,091 B2
• Filed: 05/02/2002
• Issued: 09/20/2005
• Est. Priority Date: 05/02/2002
• Status: Active Grant

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Bartels, Michael W., Wilt, Nicholas J., Gray, Scott L.
• Primary Examiner(s): LE, DIEU MINH T
• Application Number:
  US10/137,569
• Publication Number:
  US 20030208704A1
• Time in Patent Office: 1,237 Days
• Field of Search: 714/11, 714/6, 714 12- 13, 714/2, 714/48, 714764-767, 714/42, 714/45, 711/115, 711/153, 711/162, 711/173
• US Class Current: 714/11
• CPC Class Codes: G06F 11/1679 at clock signal level
• CPC Class Codes: H04L 1/22 using redundant apparatus to increase reliability

Abstract

Methods and system for facilitating a computing platform to recover quickly from transient multi-bit data failures within a run-time data memory array in a manner that is transparent to software applications executing on the computing platform. A fault-tolerant digital computing system is provided for that utilizes parallel processing lanes in a lockstep architecture. Each processing lane includes error detectors that are configured to detect multi-bit data errors in each processing lane'"'"'s memory arrays. Upon detection of a multi-bit data failure, an interrupt is generated wherein control logic software responds to the interrupt and corrects the data errors in the memory array of each processing lane.

Claims

1. A fault-tolerant digital computing system comprising:

a processor;

a first memory array and a second memory array, wherein each memory array is configured to store data across one or more memory devices;

a databus coupling the processor to each of the memory arrays;

an error detector connected to the processor and the memory arrays on the databus for receiving the data from one of the memory arrays;

a comparator connected to the error detector, the comparator configured to compare each bit of the data from one of the memory arrays to each bit of the corresponding data from the other memory array; and

a control logic module connected to the processor and the memory arrays on the databus, the control logic module configured to correct any errors in the data.

2. The system according to claim 1, wherein the error detector is further configured to provide an interrupt to the processor and the control logic module is further configured to respond to the interrupt and correct any errors in the data.

3. The system according to claim 1 wherein the comparator is further configured to provide an interrupt to the processor and the control logic module is further configured to respond to the interrupt and correct any errors in the data.

4. The system according to claim 1 wherein each memory may is configured to store at least one linear block codeword across one or more memory devices, wherein the codeword includes a dataword and a plurality of checkbits associated therewith.

5. The system according to claim 1 further comprising a plurality of redundant memory arrays.

6. A method of detecting and correcting multi-bit data failures in data for a fault-tolerant digital computer system, comprising the steps of:

generating a first copy of the data at a first processor;

providing the first copy of the data to a first error detector;

generating a second copy of the data at a second processor;

providing the second copy of the data to a second error detector;

performing a bit-by-bit cross comparison of the first and second copies of the data;

detecting a multi-bit data fault with the first or second copy of the data;

providing an interrupt to each of the first and second processors;

storing a fault-free copy of the data in a dedicated memory location,

wherein the fault-free copy is created from the first or second copy of the data; and

correcting, in response to the interrupt, the first or second copy of the data using the fault-free data copy.

7. The method according to claim 6, further comprising the step of updating a status bit in a register.

8. The method according to claim 6, further comprising the steps of:

generating a first set of checkbits at the first error detector based upon the first copy of the data; and

generating a second set of checkbits at the second error detector based upon the second copy of the data.

9. The method according to claim 8, further comprising the steps of:

using the first set of checkbits to detect and correct single bit errors in the first copy of the data; and

using the second set of checkbits to detect and correct single bit errors in the second copy of the data.

10. A system for detecting and correcting multi-bit data failures in data, the system having a first processing lane and a second processing lane, the system comprising:

a first processor associated with the first processing lane;

a second processor associated with the second processing lane;

a first memory array connected to the first processor on a databus, the first memory array configured to store a first copy of the data;

a second memory array connected to the second processor on the databus, the second memory array configured to store a second copy of the data;

a first error detector connected to the first processor and to the first and second memory arrays on the databus for receiving the first and second copies of the data;

a second error detector connected to the second processor and to the first and second memory arrays on the databus for receiving the first and second copy of the data;

a first comparator connected to the first error detector, the first comparator configured to compare each bit of the first copy of the data to each bit of the second copy of the data;

a second comparator connected to the second error detector, the second comparator configured to compare each bit of the second copy of the data to each bit of the first copy of the data;

a first control logic module connected to the first processor and to the first memory array on the databus, the first control logic module configured to correct any errors in the first copy of the data; and

a second control logic module connected to the second processor and to the second memory array on the databus, the second control logic module configured to correct any errors in the second copy of the data.

11. The system according to claim 10, wherein the first error detector is further configured to provide an interrupt to each of the first and second processors and the first control logic module is further configured to respond to the interrupt and correct any errors in the first copy of the data.

12. The system according to claim 10, wherein the second error detector is further configured to provide an interrupt to each of the first and second processors and the second control logic module is further configured to respond to the interrupt and correct any errors in the second copy of the data.

13. The system according to claim 10, wherein the first comparator is further configured to provide an interrupt to each of the first and second processors and the first control logic module is further configured to respond to the interrupt and correct any errors in the first copy of the data.

14. The system according to claim 10, wherein the second comparator is further configured to provide an interrupt to each of the first and second processors and the second control logic module is further configured to respond to the interrupt and correct any errors in the second copy of the data.

15. The system according to claim 10, wherein each memory array is configured to store at least one linear block codeword across one or more memory devices, wherein the codeword includes a dataword and a plurality of checkbits associated therewith.