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Circuits and methods for debugging an embedded processor and systems using the same

  • US 6,948,098 B2
  • Filed: 03/30/2001
  • Issued: 09/20/2005
  • Est. Priority Date: 03/30/2001
  • Status: Active Grant
First Claim
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1. A debug subsystem for testing a system-on-a-chip including an embedded processor and memory comprising:

  • at least one sub-block operable to;

    monitor a data bus between the processor and the memory to detect program selected triggering events, the triggering events including predetermined data values appearing on the data bus;

    count the number of triggering events detected; and

    when the number of triggering events reaches a program selected threshold, generating a debugging signal.

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