Circuits and methods for debugging an embedded processor and systems using the same

• US 6,948,098 B2
• Filed: 03/30/2001
• Issued: 09/20/2005
• Est. Priority Date: 03/30/2001
• Status: Active Grant

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Pillay, Sanjay Ramakrishna, Rao, Raghunath Krishna
• Primary Examiner(s): Beausoliel, Robert
• Assistant Examiner(s): Chu, Gabriel L.
• Application Number:
  US09/822,052
• Publication Number:
  US 20030051192A1
• Time in Patent Office: 1,635 Days
• Field of Search: 714/27, 714/30, 714/34, 714/35, 714/39
• US Class Current: 714/34
• CPC Class Codes: G01R 31/31701 Arrangements for setting the Unit Under Test [UUT] in a test mode
• CPC Class Codes: G01R 31/31704 Design for test; Design verification concerning scan tests G01R31/318583; computer-aided design G06F30/00
• CPC Class Codes: G01R 31/31705 Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544
• CPC Class Codes: G06F 11/2236 to test CPU or processors

Abstract

A debugging subsystem for testing a system-on-a-chip includes an embedded processor and memory and includes at least one debugging subblock monitors a bus between the processor and the memory to detect selected triggering events, counts the number of triggering events detected and when the number of triggering events reaches a predetermined threshold, generates a debugging signal.

Claims

1. A debug subsystem for testing a system-on-a-chip including an embedded processor and memory comprising:

at least one sub-block operable to;

monitor a data bus between the processor and the memory to detect program selected triggering events, the triggering events including predetermined data values appearing on the data bus;

count the number of triggering events detected; and

when the number of triggering events reaches a program selected threshold, generating a debugging signal.

2. The debug subsystem of claim 1 wherein the triggering events further include memory accesses.

3. The debug subsystem of claim 2 wherein the memory accesses are selected from the group including reads and writes.

4. The debug subsystem of claim 2 wherein the triggering events comprise memory accesses within a selected address range.

5. The debug subsystem of claim 1 wherein the debugging signal is operable to freeze a clock timing the operation of the processor.

6. The debug subsystem of claim 1 wherein the debugging signal comprises an interrupt to the processor.

7. A system on a chip comprising:

at least one processor;

a plurality of memory spaces accessible by said processor via address and data buses; and

a debug block comprising a plurality of independently programmable debug sub-blocks each for monitoring accesses to a selected one of said memories and detecting triggering events, each sub-block comprising;

a first register for setting triggering event parameters;

a second register for setting a threshold number of triggering events;

a counter for maintaining a count of detected triggering events; and

circuitry for generating a control signal when the count reaches the threshold.

8. The system of claim 7 wherein said triggering event parameters set in said first register select a selected one of the memories, select a memory access type and select an address range for detecting the access.

9. The system of claim 8 wherein said control signal freezes a dock driving said processor.

10. The system of claim 7 wherein said triggering event parameters set in said first register select a value of data accessed from the selected one of the memories.

11. The system of claim 7 wherein said control signal comprises an interrupt to said processor.

12. The system of claim 7 further comprising a second processor and said control signal comprises an interrupt to at least one of said processors.

13. The system of claim 12 wherein said second processor can access said memories and generate trigger events.

14. The system of claim 12 wherein said processor comprises a digital signal processor and said second processor comprises a microprocessor.

15. A method of debugging a single-chip system including an embedded processor and memory including a plurality of memory spaces, comprising the steps of:

selecting programmable triggering event parameters including selecting one of the memory spaces for monitoring;

monitoring transactions between the processor and the memory to detect triggering events corresponding to the selected triggering event parameters;

counting the number of triggering events detected; and

when the number of triggering events reaches a programmed predetermined threshold, generating a debugging signal.

16. The method of claim 15 wherein said step of selecting triggering event parameters further comprises the substeps of:

selecting a triggering memory access type; and

selecting a triggering address range.

17. The method of claim 15 wherein said step of monitoring comprises the step of monitoring an address bus to the memory for memory accesses meeting the triggering event parameters.

18. The method of claim 15 wherein said step of selecting triggering event parameters further comprises the substep of selecting triggering events to step through code being run by the processor.