Self-throttling error-correction buffer and method for a disc drive

• US 6,948,113 B1
• Filed: 04/20/2000
• Issued: 09/20/2005
• Est. Priority Date: 04/21/1999
• Status: Expired due to Term

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Shaver, Jimmie R.
• Primary Examiner(s): Baker, Stephen M.
• Application Number:
  US09/552,973
• Time in Patent Office: 1,979 Days
• Field of Search: 714/769, 710/52, 710/60
• US Class Current: 714/769
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0674 Disk device
• CPC Class Codes: G11B 20/10527 Audio or video recording; Data buffering arrangements G11B20/12 - G11B20/18 take precedence
• CPC Class Codes: G11B 20/18 Error detection or correction; Testing , e.g. of drop-outs
• CPC Class Codes: G11B 2020/1062 Data buffering arrangements, e.g. recording or playback buffers
• CPC Class Codes: G11B 2020/10787 parameters, e.g. for decoding or encoding

Abstract

A method and apparatus for an error-correction buffer having self-throttling data burst control in a disc drive. One aspect of the present invention provides an arbitration-throttling control circuit for use in a disc drive to self-throttle the data transfer of an error-correction buffer. The arbitration-throttling control circuit includes a control circuit having an error-correction buffer interface and a disc-drive main buffer memory interface for controlling data transfer from the error-correction buffer to a disc-drive main buffer in a plurality of data bursts. The control circuit arbitrates for access to transfer data into the disc-drive main buffer such that a series of data bursts from the error-correction buffer to the disc-drive main buffer are spread substantially evenly over a period of time.

Claims

1. A circuit comprising:

a first buffer interface that monitors availability of data from a first buffer;

a second buffer interface that controls data transfer from the first buffer to a second buffer in a plurality of data bursts, each data burst having a predetermined burst quantity of data; and

a control circuit, coupled to the interfaces that arbitrates for access to transfer data into the second buffer such that a series of data bursts totaling a predetermined quantity of data from the first buffer to the second buffer is spread substantially evenly over a period of time substantially equal to a transfer time of the predetermined quantity of data into the first buffer, wherein the predetermined quantity of data is larger than the burst quantity of data.

2. The circuit of claim 1, wherein the circuit, upon an indication that the predetermined quantity of data from the first buffer is available for transfer, provides one arbitration request to obtain data transfer access to the second buffer from the first buffer.

3. The circuit of claim 1, wherein the predetermined quantity of data includes (512) data bytes, each one of the data bursts of the burst quantity of data includes sixty-four data bytes, and a buffer controller enables up to one additional data burst to occur each time period substantially equal to a time needed for sixty-four data bytes to be transferred from the disc.

4. The circuit of claim 3, wherein the buffer controller further comprises:

a byte-clock counter that is clocked based on a frequency of data transfer from the disc, and that produces an output pulse based on the byte-clock counter counting a predetermined number of clock cycles;

an arbitration request counter, operatively coupled to the byte-clock counter, that is incremented by the output pulse of the byte-clock counter, that is decremented when a disc-channel arbitration grant is obtained, and that produces a disk-channel arbitration request if the arbitration request counter has a value of one or more; and

an arbitration logic, operatively coupled to the arbitration request counter, that receives disc-channel arbitration requests and provides disc channel arbitration grants, in order to spread data bursts from the error-correction buffer to the disc-drive main buffer memory over a period of time substantially equal to the sector transfer time.

5. The circuit of claim 4, wherein the buffer controller further comprises:

a reset circuit configured to reset the byte-clock counter based on a data availability of data out of the error-correction buffer.

6. The circuit of claim 4, wherein each one of the data bursts includes N data bytes, and the arbitration request counter is incremented once for each N byte-clock cycles.

7. The circuit of claim 4, wherein a sector transfer includes (512) data bytes, each one of the data bursts includes sixty-four data bytes, and the arbitration request counter is incremented once for each time period substantially equal to a time needed for sixty-four data bytes to be transferred from the disc.

8. An apparatus comprising:

a first data store coupled to receive data at a first data rate;

wherein the apparatus is configured to transfer data bursts totaling an amount of received data from the first data store that are spread substantially evenly over a period of time substantially equal to a transfer time of the predetermined quantity of data into the first data store wherein the amount of received data is larger than the burst quantity of data.

9. The apparatus of claim 8 further comprising:

an arbitration-throttling control circuit; and

a second data store, wherein the arbitration-throttling control circuit, upon an indication that the amount of received data from the first data store is available for transfer, provides one arbitration request to obtain data transfer access to the second data store from the first data store for each time period substantially equal to a time needed for the burst quantity of data to be transferred.

10. The apparatus of claim 9, wherein the amount of received data includes (512) data bytes, each one of the data bursts of the burst quantity of data includes sixty-four data bytes, and the arbitration-throttling control circuit enables up to one additional data burst to occur each time period substantially equal to a time needed for sixty-four data bytes to be transferred from a storage medium.

11. The apparatus of claim 9, wherein the arbitration-throttling control circuit further comprises:

a byte-clock counter that is clocked based on a rate of data transfer from the storage medium, and that produces an output pulse based on the byte-clock counter counting a predetermined number of clock cycles;

an arbitration request counter, operatively coupled to the byte-clock counter, that is incremented by the output pulse of the byte-clock counter, that is decremented when a disc-channel arbitration grant is obtained, and that produces a disc-channel arbitration request if the arbitration request counter has a value of one or more; and

an arbitration logic, operatively coupled to the arbitration request counter, that receives disc-channel arbitration requests and provides disc-channel arbitration grants, in order to spread data bursts from the first data store to the second data store over a period of time substantially equal to the transfer time of the received data.

12. The apparatus of claim 11, wherein the arbitration-throttling control circuit further comprises:

a reset circuit configured to reset the byte-clock counter based on a data transfer count of data out of the first data store.

13. The apparatus claim 11, wherein each one of the data bursts includes N data bytes, and the arbitration request counter is incremented once for each N byte-clock cycles.

14. The apparatus of claim 11, wherein a sector transfer includes (512) data bytes, each one of the data bursts includes sixty-four data bytes, and the arbitration request counter is incremented once for each time period substantially equal to a time needed for sixty-four data bytes to be transferred from the disc.

15. The apparatus of claim 11, further comprising:

a data-handling system operatively coupled to at least read data from the disc, the data-handling system further comprising;

one or more data processors;

one or more memories operatively coupled to each one of the one or more data processors; and

at least one input/output system coupled to at least one of the one or more data processors to receive input data and to supply output data.

16. The apparatus of claim 8 further comprising a second data store coupled to receive the data bursts from the first data store, each data burst having a burst data rate higher than the first data rate.

17. A method comprising steps of:

(a) receiving data into first buffer at a first data rate; and

(b) transferring the data out of the first buffer in a plurality of data bursts, each one of the data bursts having a burst data rate that is higher than the first data rate, the data bursts having a timing based on the first data rate.

18. The method according to claim 17, further comprising a step of:

(c) performing an error correction operation on the data within the first buffer before performing the transferring step (b).

19. The method according to claim 17, wherein the transferring step (b) further comprises:

(b)(i) deriving a burst-enable pulse by dividing a clock signal by a predetermined value, wherein the clock signal is based an the first data rate, and the predetermined value is based on an amount of data in one of the plurality of data bursts.

20. The method according to claim 17, wherein the transferring step (b) further

comprises:

(b)(ii) upon an indication that the sector quantity of data from the first buffer is available for transfer, providing an arbitration request to obtain data transfer access to a second buffer from the first buffer for each time period substantially equal to a time needed for a burst quantity of data to be transferred.

21. A disc drive system comprising:

a base plate;

a rotatable disc mounted to the base plate;

an actuator, the actuator including a transducer mounted to the actuator in transducing relation to the disc;

buffer memory means operatively coupled to the transducer for self-throttling data bursts of an error-correction buffer.