Methods and apparatus for characterizing board test coverage

• US 6,948,140 B2
• Filed: 09/01/2002
• Issued: 09/20/2005
• Est. Priority Date: 09/01/2002
• Status: Expired due to Fees

• Current Assignee: Agilent Technologies, Inc.
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Hird, Kathleen J., Ramos, Erik A., Parker, Kenneth P.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): TAT, BINH C
• Application Number:
  US10/233,767
• Publication Number:
  US 20040044973A1
• Time in Patent Office: 1,115 Days
• Field of Search: 716 1- 6, 716/18, 702179-182, 702/117, 702/118, 714 30- 33, 714/726, 707/3
• US Class Current: 716/112
• CPC Class Codes: G01R 31/2806 Apparatus therefor, e.g. test stations, drivers, analysers, conveyors G01R31/2805, G01R31/281, G01R31/2818 take precedence
• CPC Class Codes: G01R 31/2834 Automated test systems [ATE]; using microprocessors or computers G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736

Abstract

Disclosed are methods and apparatus for characterizing board test coverage. In one method, potentially defective properties are enumerated for a board, without regard for how the potentially defective properties might be tested. For each potentially defective property enumerated, a property score is generated. Each property score is indicative of whether a test suite tests for a potentially defective property. Property scores are then combined to characterize board test coverage for the test suite.

Claims

1. A method for characterizing board test coverage, comprising:

a) enumerating potentially defective properties for a board, without regard for how the potentially defective properties might be tested;

b) for each potentially defective property enumerated, generating a property score that is indicative of whether a test suite tests for the potentially defective property; and

c) combining property scores to characterize board test coverage for the test suite.

2. The method of claim 1, wherein potentially defective properties are enumerated, at least in part, by parsing a netlist for the board.

3. The method of claim 1, wherein potentially defective properties are enumerated, at least in part, by parsing a bill of materials for the board.

4. The method of claim 1, wherein potentially defective properties are enumerated, at least in part, by parsing CAD data for the board.

5. The method of claim 1, wherein the potentially defective properties enumerated comprise component properties and connection properties.

6. The method of claim 5, wherein the potentially defective properties enumerated further comprise intangible properties.

7. The method of claim 6, wherein one intangible property is programming correctness.

8. The method of claim 1, wherein the potentially defective properties enumerated comprise at least the following component properties:

presence, correctness, orientation, liveness, and alignment.

9. The method of claim 1, wherein the potentially defective properties enumerated comprise at least one component property selected from the group consisting of:

presence, correctness, orientation, liveness, and alignment.

10. The method of claim 1, wherein different potentially defective properties are enumerated for different component types.

11. The method of claim 1, wherein different potentially defective properties are enumerated for different package types.

12. The method of claim 1, wherein the potentially defective properties enumerated comprise at least the following connection properties:

shorts, opens, and quality.

13. The method of claim 1, wherein the potentially defective properties enumerated comprise at least one connection property selected from the group consisting of:

shorts, opens, and quality.

14. The method of claim 1, wherein property scores comprise numerical equivalents for:

Fully Tested, Partially Tested, and Untested.

15. The method of claim 1, wherein combining property scores to characterize board test coverage comprises combining two or more property scores using a MAX function when i) a potentially defective property is tested by two or more tests in the test suite, and ii) two or more property scores are generated for the same potentially defective property.

16. The method of claim 1, wherein combining property scores to characterize board test coverage comprises, for a given component, combining the component'"'"'s property scores to generate a component score.

17. The method of claim 1, wherein combining property scores to characterize board test coverage comprises, for a given connection, combining the connection'"'"'s property scores to generate a connection score.

18. The method of claim 1, wherein combining property scores to characterize board test coverage comprises:

a) combining all component property scores to generate a board component score; and

b) combining all connection property scores to generate a board connection score.

19. Apparatus for characterizing board test coverage, comprising:

a) computer readable storage media; and

b) computer readable program code, stored on the computer readable storage media, comprising;

i) program code for building a list of potentially defective properties for a board;

said program code A) parsing descriptive information for the board to extract component and connection information for the board, and B) associating potentially defective properties with the extracted component and connection information;

ii) program code for parsing a test suite and extracting test objects therefrom;

each test object comprising A) details of a test, and B) a list of components and connections that are tested by the test;

iii) program code for associating the test objects with entries in the list of potentially defective properties, by identifying common components and connections in each; and

iv) program code for assigning property scores to the potentially defective properties in said list of potentially defective properties, in response to whether tests in the associated test objects test for the potentially defective properties.

20. The apparatus of claim 19, wherein the descriptive information for the board is an XML topology file for the board.

21. The apparatus of claim 19, wherein at least some connection and connection information is indicated by pin and node information.

22. The apparatus of claim 19, wherein:

a) one potentially defective property that may be associated with extracted connection information is a short property; and

b) the program code associates the short property of a connection with zero or more shorts by assessing the proximity of the connection to other pins and/or nodes identified in the board'"'"'s descriptive information.

23. The apparatus of claim 19, wherein the program code for building a list of potentially defective properties associates different potentially defective properties with different component types.

24. The apparatus of claim 19, wherein the program code for building a list of potentially defective properties associates different potentially defective properties with different package types.

25. The apparatus of claim 19, wherein the test objects are XML objects.

26. The apparatus of claim 19, wherein the potentially defective properties comprise at least one component property selected from the group consisting of:

presence, correctness, orientation, liveness, and alignment.

27. The apparatus of claim 19, wherein the potentially defective properties comprise at least one connection property selected from the group consisting of:

shorts, opens, and quality.

28. Apparatus for characterizing board test coverage, comprising:

a) means for enumerating potentially defective properties for a board, without regard for how the potentially defective properties might be tested;

b) means for determining and scoring, in relation to each potentially defective property enumerated, whether a test suite tests for the potentially defective property; and

c) means for combining scores to characterize board test coverage for the test suite.

29. A method for comparing board test coverage for two test suites, comprising:

a) enumerating potentially defective properties for a board, without regard for either of the test suites;

b) for each test suite, scoring whether the test suite tests for the potentially defective properties enumerated; and

c) comparing scores for the two test suites.

30. A method as in claim 29, wherein the potentially defective properties enumerated comprise:

a) component properties selected from the properties;

presence, correctness, orientation, liveness, and alignment; and

b) connection properties selected from the properties;

shorts, opens, and quality.

31. Apparatus for characterizing board test coverage, comprising:

a) computer readable storage media; and

b) computer readable program code, stored on the computer readable storage media, comprising program code for i) parsing a test suite and a list of potentially defective properties for a board, and ii) assigning property scores to potentially defective properties in response to whether the test suite tests for the potentially defective properties.

32. The apparatus of claim 31, wherein the property scores comprise numerical equivalents for:

Fully Tested, Partially Tested, and Untested.

33. The apparatus of claim 31, wherein the computer readable program code further comprises program code for combining two or more property scores using a MAX function when a potentially defective property is tested by two or more tests in the test suite and two or more property scores exist for the same potentially defective property.

34. The apparatus of claim 31, wherein the computer readable program code further comprises program code for combining a given component'"'"'s property scores to generate a component score for the given component.

35. The apparatus of claim 31, wherein the computer readable program code further comprises program code for combining a given connection'"'"'s property scores to generate a connection score for the given connection.

36. The apparatus of claim 31, wherein the computer readable program code further comprises program code for i) combining all component property scores to generate a board component score, and ii) combining all connection property scores to generate a board connection score.