Apparatus and methods for determining critical area of semiconductor design data

• US 6,948,141 B1
• Filed: 10/24/2002
• Issued: 09/20/2005
• Est. Priority Date: 10/25/2001
• Status: Active Grant

• Current Assignee: Kla-Tencor Technologies Corporation (KLA Corporation)
• Original Assignee: Kla-Tencor Technologies Corporation (KLA Corporation)
• Inventors: Federov, Vladimir D., Song, Li, Satya, Akella V. S.
• Primary Examiner(s): Whitmore, Stacy A.
• Assistant Examiner(s): Bowers, Brandon
• Application Number:
  US10/281,427
• Time in Patent Office: 1,062 Days
• Field of Search: 716/4, 716/18, 716/21
• US Class Current: 716/52
• CPC Class Codes: G01R 31/318364 as a result of hardware simulation, e.g. in an HDL environment computer-aided simulation of circuits G06F30/3308
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01J 2237/2817 Pattern inspection

Abstract

Disclosed are mechanisms for efficiently and accurately calculating critical area. In general terms, a method of determining a critical area for a semiconductor design layout is disclosed. The critical area is utilizable to predict yield of a semiconductor device fabricated from such layout. A semiconductor design layout having a plurality of features is first provided. The features have a plurality of polygon shapes which include nonrectangular polygon shapes. Each feature shape has at least one attribute or artifact, such as a vertex or edge. A probability of fail function is calculated based on at least a distance between two feature shape attributes or artifacts. By way of example implementations, a distance between two neighboring feature edges (or vertices) or a distance between two feature edges (or vertices) of the same feature is first determined and then used to calculate the probability of fail function. In a specific aspect, the distances are first used to determine midlines between neighboring features or midlines within a same feature shape, and the midlines are then used to determine the probability of fail function. A critical area of the design layout is then determined based on the determined probability of fail function. In specific implementations, the defect type is a short type defect or an open type defect. In a preferred implementation, the features may have any suitable polygonal shape, as is typical in a design layout.

Claims

1. A method of for determining a critical area of at least a portion of a design layout, the design layout comprising design shapes, the design shapes comprising design shape artifacts, the method comprising:

determining at least one critical inner boundary based on at least one design shape artifact of at least one design shape;

determining at least one critical outer boundary based on at least one design shape artifact of at least one design shape; and

based on the at least one critical inner boundary and the at least one critical outer boundary, determining the critical area for a particular defect type,

wherein the critical outer boundary is located along a midline between two adjacent design shapes and the critical inner boundary is located along a midline between a pair of outer boundaries.

2. A method as recited in claim 1, wherein the design shapes can be any polygon shape.

3. A method as recited in claim 1, wherein the particular type of defect is a short type defect.

4. A method as recited in claim 1, wherein the particular type of defect is an open type defect.

5. A method as recited in claim 1, wherein determining the at least one critical inner and outer boundaries comprises:

for each vertex of a feature, determining and adding a midpoint of a line from such feature to a closest feature to a midpoint list and;

merging the midpoint list into a plurality of critical inner and outer boundaries.

6. A method as recited in claim 5, wherein determining the critical area comprises:

dividing the design layout into a plurality of simple regions based on the determined inner and outer boundaries;

determining a probability of fail curve for each simple region;

summing the probability of fail curves for the simple regions, weighted by an area size of the each simple region to obtain a total probability of fail curve;

providing a defect size distribution curve; and

defining the critical area as an integration of the total probability of fail curve convoluted with the defect size distribution curve.

7. A method as recited in claim 1, wherein determining the critical inner and outer boundaries and determining the critical area are performed without iteration of a design shape artifact'"'"'s position or a defect size of a defect having the particular defect type.

8. A computer program product for determining a critical area of at least a portion of a design layout, the design layout comprising design shapes, the design shapes comprising design shape artifacts, the computer program product comprising:

at least one computer readable medium;

computer program instructions stored within the at least one computer readable product operable to;

determine at least one critical inner boundary based on at least one design shape artifact of at least one design shape;

determine at least one critical outer boundary based on at least one design shape artifact of at least one design shape, wherein the critical outer boundary is located along a midline between two adjacent design shapes and the critical inner boundary is located along a midline between a pair of outer boundaries; and

based on the at least one critical inner boundary and the at least one critical outer boundary, determine the critical area for a particular defect type.

9. A computer program product as recited in claim 8, wherein determining the at least one critical inner and outer boundaries comprises:

for each vertex of a feature, determining and adding a midpoint of a line from such feature to a closest feature to a midpoint list and;

merging the midpoint list into a plurality of critical inner and outer boundaries.

10. A computer program product as recited in claim 9, wherein determining the critical area comprises:

dividing the design layout into a plurality of simple regions based on the determined inner and outer boundaries;

determining a probability of fail curve for each simple region;

summing the probability of fail curves for the simple regions, weighted by an area size of the each simple region to obtain a total probability of fail curve;

providing a defect size distribution curve; and

defining the critical area as an integration of the total probability of fail curve convoluted with the defect size distribution curve.

11. A computer program product as recited in claim 8, wherein determining the critical inner and outer boundaries and determining the critical area are performed without iteration of a design shape artifact'"'"'s position or a defect size of a defect having the particular defect type.

12. An inspection system for determining a critical area of at least a portion of a design layout, the design layout comprising design shapes, the design shapes comprising design shape artifacts, the system comprising:

beam generator for generating an electron beam towards a semiconductor device or test structure;

a detector for detecting secondary and/or backscattered electrons from the semiconductor device or test structure and generating a detected signal, the secondary or backscattered electrons being in response to the generated electron beam; and

a processor arranged to;

determine at least one critical inner boundary based on at least one design shape artifact of at least one design shape;

determine at least one critical outer boundary based on at least one design shape artifact of at least one design shape, wherein the critical outer boundary is located along a midline between two adjacent design shapes and the critical inner boundary is located along a midline between a pair of outer boundaries;

based on the at least one critical inner boundary and the at least one critical outer boundary, determine the critical area for a particular defect type;

cause the beam generator and detector to direct an incident electron beam onto a plurality of test structures formed from the design layout to thereby cause the detector to generate a plurality of detected signals, the test structures being disposed on a product wafer having a plurality of semiconductor product devices;

determine a defect density for each test structure based on the detected signals; and

calculate yield of the product wafer based on the determined defect density and calculated critical area of each test structure.

13. An inspection system as recited in claim 12, wherein the design shapes include a nonrectangular shape.

14. An inspection system as recited in claim 12, wherein the particular type of defect is a short type defect.

15. An inspection system as recited in claim 12, wherein the particular type of defect is an open type defect.

16. An inspection system as recited in claim 12, wherein determining the at least one critical inner and outer boundaries comprises:

for each vertex of a feature, determining and adding a midpoint of a line from such feature to a closest feature to a midpoint list and;

merging the midpoint list into a plurality of critical inner and outer boundaries.

17. An inspection system as recited in claim 16, wherein determining the critical area comprises:

dividing the design layout into a plurality of simple regions based on the determined inner and outer boundaries;

determining a probability of fail curve for each simple region;

summing the probability of fail curves for the simple regions, weighted by an area size of the each simple region to obtain a total probability of fail curve;

providing a defect size distribution curve; and

defining the critical area as an integration of the total probability of fail curve convoluted with the defect size distribution curve.

18. An inspection system as recited in claim 12, wherein determining the critical inner and outer boundaries and determining the critical area are performed without iteration of a design shape artifact'"'"'s position or a defect size of a defect having the particular defect type.