Apparatus and methods for determining critical area of semiconductor design data
First Claim
1. A method of for determining a critical area of at least a portion of a design layout, the design layout comprising design shapes, the design shapes comprising design shape artifacts, the method comprising:
- determining at least one critical inner boundary based on at least one design shape artifact of at least one design shape;
determining at least one critical outer boundary based on at least one design shape artifact of at least one design shape; and
based on the at least one critical inner boundary and the at least one critical outer boundary, determining the critical area for a particular defect type, wherein the critical outer boundary is located along a midline between two adjacent design shapes and the critical inner boundary is located along a midline between a pair of outer boundaries.
1 Assignment
0 Petitions
Accused Products
Abstract
Disclosed are mechanisms for efficiently and accurately calculating critical area. In general terms, a method of determining a critical area for a semiconductor design layout is disclosed. The critical area is utilizable to predict yield of a semiconductor device fabricated from such layout. A semiconductor design layout having a plurality of features is first provided. The features have a plurality of polygon shapes which include nonrectangular polygon shapes. Each feature shape has at least one attribute or artifact, such as a vertex or edge. A probability of fail function is calculated based on at least a distance between two feature shape attributes or artifacts. By way of example implementations, a distance between two neighboring feature edges (or vertices) or a distance between two feature edges (or vertices) of the same feature is first determined and then used to calculate the probability of fail function. In a specific aspect, the distances are first used to determine midlines between neighboring features or midlines within a same feature shape, and the midlines are then used to determine the probability of fail function. A critical area of the design layout is then determined based on the determined probability of fail function. In specific implementations, the defect type is a short type defect or an open type defect. In a preferred implementation, the features may have any suitable polygonal shape, as is typical in a design layout.
135 Citations
18 Claims
-
1. A method of for determining a critical area of at least a portion of a design layout, the design layout comprising design shapes, the design shapes comprising design shape artifacts, the method comprising:
-
determining at least one critical inner boundary based on at least one design shape artifact of at least one design shape;
determining at least one critical outer boundary based on at least one design shape artifact of at least one design shape; and
based on the at least one critical inner boundary and the at least one critical outer boundary, determining the critical area for a particular defect type, wherein the critical outer boundary is located along a midline between two adjacent design shapes and the critical inner boundary is located along a midline between a pair of outer boundaries. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. A computer program product for determining a critical area of at least a portion of a design layout, the design layout comprising design shapes, the design shapes comprising design shape artifacts, the computer program product comprising:
-
at least one computer readable medium;
computer program instructions stored within the at least one computer readable product operable to;
determine at least one critical inner boundary based on at least one design shape artifact of at least one design shape;
determine at least one critical outer boundary based on at least one design shape artifact of at least one design shape, wherein the critical outer boundary is located along a midline between two adjacent design shapes and the critical inner boundary is located along a midline between a pair of outer boundaries; and
based on the at least one critical inner boundary and the at least one critical outer boundary, determine the critical area for a particular defect type. - View Dependent Claims (9, 10, 11)
-
-
12. An inspection system for determining a critical area of at least a portion of a design layout, the design layout comprising design shapes, the design shapes comprising design shape artifacts, the system comprising:
-
beam generator for generating an electron beam towards a semiconductor device or test structure;
a detector for detecting secondary and/or backscattered electrons from the semiconductor device or test structure and generating a detected signal, the secondary or backscattered electrons being in response to the generated electron beam; and
a processor arranged to;
determine at least one critical inner boundary based on at least one design shape artifact of at least one design shape;
determine at least one critical outer boundary based on at least one design shape artifact of at least one design shape, wherein the critical outer boundary is located along a midline between two adjacent design shapes and the critical inner boundary is located along a midline between a pair of outer boundaries;
based on the at least one critical inner boundary and the at least one critical outer boundary, determine the critical area for a particular defect type;
cause the beam generator and detector to direct an incident electron beam onto a plurality of test structures formed from the design layout to thereby cause the detector to generate a plurality of detected signals, the test structures being disposed on a product wafer having a plurality of semiconductor product devices;
determine a defect density for each test structure based on the detected signals; and
calculate yield of the product wafer based on the determined defect density and calculated critical area of each test structure. - View Dependent Claims (13, 14, 15, 16, 17, 18)
-
Specification